Cambridge is doing a challenge to get the fastest possible switch design for their netfpga hardware.
http://www.cl.cam.ac.uk/research/srg/netfpga/challenge2017/ Their basic proposed test suite is pretty bare-bones and doesn't touch upon the congestion issue, really. Just forwarding behaviors. Two+ ports into one or more ports, is where smarter queue management gets needed (as well as macaddr CAM), but then what you measure as "latency" becomes rather fungible and harder to define than "tx to rx". Even their third test is still one to one, essentially. I do think a good open source and fast cut-through switch design would be a great building block to start with, particularly if they can nail it for small packets. All it's gotta do is timestamp on receive (for codel) from a fairly unified clock, at the head, and hash on L4 headers (fq_codel) by the end, but that's not within the scope of the contest design parameters, and I imagine folk will engineer to the test to get the last ns out instead of passing those extra 8 bytes along fore and aft. I wish I had time to tackle this, and my verilog was less rusty, and I wasn't such a greying grad student myself. Maybe some team from here is already on this, laboring in secret... It looks like a great contest, I'd love to be plotting behaviors with flent... with ports going at line rates of 10,000, 1000, 100.... of whatever they come up with. -- Dave Täht Let's go make home routers and wifi faster! With better software! http://blog.cerowrt.org _______________________________________________ Bloat mailing list [email protected] https://lists.bufferbloat.net/listinfo/bloat
