On Mon, Jul 23, 2018 at 5:52 AM Mikael Abrahamsson <swm...@swm.pp.se> wrote: > > On Sat, 21 Jul 2018, Jonathan Morton wrote: > > > An example of such a situation would be sparse flows in DRR++, which is > > a key part of fq_codel and Cake. So to implement DRR++ using timing > > wheels, you have to choose your scheduling horizon carefully so as to > > minimise the delay to sparse packets. > > At the spring IETF, there was talk from IEEE person about using ethernet > pause frames to get senders to stop talking for a while. My understanding > was that this was on microsecond scale or even nanosecond time scales. > > One of the mentions in the presentation was on slide 10 about > "fat-buffered router". In the data center, these are kind of going away, > because on-die memory is small and rates are high. A 64x100GE forwarding > asic might have 16MB of buffer, which is very little buffer for the kind > of bit rates we're talking here. > > https://www.youtube.com/watch?v=sJMvAqEQCBE 1h44m in (proposed IEEE > 802.1Qcz work) is the one I am thinking of.
OK, I watched a bit of that. Lot of handwaving. Prior to that I fast forwarded past BB's l4s thing and looked a little at PSS, which essentially looked like it was doing FQ between dscp marks.... I think the ietf should just rename itself to being DCTF (the data center task force) and let some other org arise to take care of the internet. > Wonder how this would interact with the timing wheel proposed by Van Jacobson. FIFO queues remain cheap. I keep hitting reload hoping the video to the talk was up. > Jacobson? > > -- > Mikael Abrahamsson email: swm...@swm.pp.se > _______________________________________________ > Bloat mailing list > Bloat@lists.bufferbloat.net > https://lists.bufferbloat.net/listinfo/bloat -- Dave Täht CEO, TekLibre, LLC http://www.teklibre.com Tel: 1-669-226-2619 _______________________________________________ Bloat mailing list Bloat@lists.bufferbloat.net https://lists.bufferbloat.net/listinfo/bloat