Pádraig Brady <p...@draigbrady.com> writes: Thanks for checking that. Torbjorn you seem to be interploating from your 3.3 GHz Sandy bridge to my 2.1GHz i3-2310M Sandy Bridge, but it might not be linear due to cache, turbo boost, mem bandwidth, ... It should be linear in clock frequency, yes.
The factor program's working set (code and data) is tiny. Things should fit in L1 caches. We have a prime table, but it is smaller than L1D (at about 10 kB). All Sandy bridges in the world have the same L1 cache sizes. Mem bandwidth is therefore irrelevamt, and so is higher-level caches. "Turbo boost" is relevant, but I have that switched off since I am quite fond of reproducible benchmarking results. -- Torbjörn
