Pete French <[EMAIL PROTECTED]> writes: >> Thread B on Processor B sees isCreated = 1, but still has a stale >> value (nil) for 'theInstance' in its L1/L2 memory cache >> and returns the nil. > > I can't imagine that this would ever happen - if processors in an SMP > system had independent caches such that they saw different cached values > for the same location then it wouldnt work at all. The cache consistency > mechanism is there to ensure that this never happens, so it shouldnt be an > issue. > Well, I think that consistency is only guarenteed when locking is used appropriately. For example in the paper:
Impact of Java Memory Model on Out-of-Order Multiprocessors by Tulika Mitra, Abhik Roychoudhury, Qinghua Shen from School of Computing National University of Singapore The examine the old an new proposed Java Memory Model. They claim that: [BEGIN QUOTE] Thread 1 Thread 2 Write a,1 read volatile v Write a,2 read a Write volatile v, 1 assuming v and a are initialized to 0, it is possible to read v=1 and a=1 in the second thread [END QUOTE] They are discussing the current Java Memory Model. But I am trying to find more documentation on multi processor architectures to really understand what is happening. Wim Oudshoorn. _______________________________________________ Bug-gnustep mailing list [email protected] http://lists.gnu.org/mailman/listinfo/bug-gnustep
