Damien Zammit, le mar. 30 mars 2021 13:58:30 +1100, a ecrit:
> +AC_ARG_ENABLE([apic],
> + AS_HELP_STRING([--enable-apic], [LAPIC/IOAPIC support (ix86-only); enabled
> by default]))
I don't think we want to enable it by default for now :)
(that will allow to just commit the support and be done with integrating
that, even before userland is ready to route IRQs according to ACPI)
> @@ -27,21 +31,31 @@
> * On entry, %eax contains the irq number.
> */
> ENTRY(interrupt)
> +#ifdef APIC
> + cmpl $255,%eax /* was this a spurious intr? */
> + je _null_eoi /* if so, null eoi handler */
> +#endif
> + /* Align the stack to nearest 16 byte boundary */
> + pushl %ebp /* save base pointer */
> + movl %esp,%ebp /* move to new stack frame */
> + subl $8,%esp /* go halfway to aligned stack */
> + andl $-16,%esp /* align stack */
> +
> pushl %eax /* save irq number */
> movl %eax,%ecx /* copy irq number */
> shll $2,%ecx /* irq * 4 */
> call spl7 /* set ipl */
> movl EXT(iunit)(%ecx),%edx /* get device unit number */
> + pushl $0 /* keep stack aligned */
> pushl %eax /* push previous ipl */
> pushl %edx /* push unit number */
> call *EXT(ivect)(%ecx) /* call interrupt handler */
Err, no, that won't fly actually. See hardclock's parameter usage, it
does need to access the return address and registers to properly account
timing. So in the end the realign would need to be done before this.
Possibly simply by shifting the interrupt stack a bit.
> +#else
> + cmpl $16,%ecx /* was this a low ISA intr? */
> + jl _isa_eoi /* no, must be PCI */
> + jmp _done /* NB: let irq_acknowledge handle pci
> EOI */
Rather jge than jl+jmp?
> +void
> +picdisable(void)
> +{
> + asm("cli");
> +
> + /*
> + ** Disable PIC
> + */
> + outb ( 0xa1, 0xff );
> + outb ( 0x21, 0xff );
You have macros for these in pic.h: PIC_MASTER_OCW, PIC_SLAVE_OCW,
PICM_MASK, PICS_MASK.
Samuel
