Hi Damien,
On 26/09/2026 02:12, Damien Zammit wrote:
Hey Mike,
I wrote this last year, I think its a bug in qemu:
Does this fix your issue?
Author: Damien Zammit <[email protected]>
Date: Sun Jun 22 21:45:26 2025 +1000
hw/i386/pc_piix.c: Add IRQs 14,15 as MADT overrides
When PIIX3 IDE is used, these two interrupts are
active-low level-triggered but are not set as MADT overrides.
Since the default for legacy interrupts is on rising edge,
these two extra MADT isa irq overrides are needed.
Signed-off-by: Damien Zammit <[email protected]>
If Qemu supplied the 2 overrides then that would allow gnumach to
revert legacy IRQ14 and IRQ15 to their default status thus removing the
need to explicitly code them as active low and level triggered ? I don't
think it would help with getting my hardware to work though which works
only when the APIC is configured as active high and edge triggered.
The confusing thing, to me anyway, is that the same version of NetBSD
functions normally running on Qemu and on my hardware whereas Hurd works
with Qemu only when the APIC pin is active low/level triggered and on my
hardware when active high/edge triggered. There is something here that
I'm failing to grasp.
I don't seem to be very capable of too much context switching myself
these days. Once I've finished my stab at UEFI then I'll get back to
this with a complete review of what works, what doesn't and why, and
then seek some help getting it sorted.
Thanks for the help. Cheers,
Mike.
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index ea7572e783..7320563890 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -181,6 +181,11 @@ static void pc_init1(MachineState *machine, const
char *pci_type)
}
}
+ /* Add IRQ 14,15 to MADT overrides for PIIX3 IDE */
+ if (pcmc->pci_enabled) {
+ x86ms->pci_irq_mask |= (1<<14) | (1<<15);
+ }
+
pc_machine_init_sgx_epc(pcms);
x86_cpus_init(x86ms, pcmc->default_cpu_version);
Damien
On 26/9/26 10:39 am, Damien Zammit wrote:
Hi Mike,
Did you end up sending mail to NetBSD to ask about rump?
I can't find the thread.
It might be worth asking them about this particular issue as well.
I read somewhere on netbsd's mailing list archives that they
have to use -M q35 as well for qemu to work correctly (which
basically bypasses the piix3 ide controller).
Damien
On 8/9/26 10:11 pm, Michael Kelly wrote:
2) Perhaps the more difficult issue relates to the IOAPIC interrupt
configuration. Looking at gnumach/i386/i386at/ioapic.c,
ioapic_configure() configures pins 14 and 15 with level triggering and
active low. I think that historically these were configured as legacy
IRQs having edge triggering and active high but were changed to allow
Qemu IDE on piix3 to work. On my hardware machine, these pins need to be
configured as legacy pins (active high/edge triggered).
I'd have expected that Qemu would emulate pins 14 and 15 as active
high/edge triggered but it seems not as booting a virtual machine
(i440fx) with my changes does not work correctly and has interrupt
loss/timeout issues. The strange thing is that booting NetBSD with the
same virtual machine works correctly and yet that seems to configure the
interrupt as active high/edge triggered. I can't explain this
inconsistency at the moment.
Can anyone can shed any light on the interrupt configuration issue?
Cheers,
Mike.
