Follow-up Comment #4, bug #18963 (project make):
Is this really the way it is supposed to work. It didn't work like that in
previous releases of make. To exemplify, I want a makefile with automatic
dependencies. If I write it like this:
--- Makefile ---
all: hello
include hello.d
%.d: %.c
$(CC) -M -MG -MT "$*.o $@" -MF $@ $<
------
--- hello.c ---
#include <stdio.h>
int main()
{
printf("Hello\n");
}
------
I will get the following output if hello.d does not exist.
Makefile:6: hello.d: No such file or directory
cc -M -MG -MT "hello.o hello.d" -MF hello.d hello.c
cc -c -o hello.o hello.c
cc hello.o -o hello
I want to get rid of the error message (because it isn't an error) so I put a
"-" infront of the include directive in the makefile. Everything looks fine
until I try to include a file that does not exist (e.g. hello.h) in hello.c.
Then I will get the following output:
cc -M -MG -MT "hello.o hello.d" -MF hello.d hello.c
The compilation just stops with no error message. The exit code is 2 if one
checks it. What I expect is a row like:
make: *** No rule to make target `hello.h', needed by `hello.d'. Stop.
This was the way it worked in earlier releases of make. Maybe there is
another way around this but I cannot find it.
Regards,
Tobias
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