The following reply was made to PR kernel/6517; it has been noted by GNATS.

From: Marco Pfatschbacher <[email protected]>
To: [email protected]
Cc:  
Subject: Re: kernel/6517: X rendering errors and inteldrm panic on 82865G
Date: Sat, 29 Jan 2011 01:35:02 +0100

 On Fri, Nov 26, 2010 at 08:17:04PM +0100, Marco Pfatschbacher wrote:
 > >Description:
 > The latest intel(4) and inteldrm(4) cause heavy rendering errors and
 > panic the Kernel after a Ctrl+Alt+Backspace.
 > 
 > >How-To-Repeat:
 > Open xterm and move it around, kill Xserver.
 > 
 > >Fix:
 
 After cursing myself for not using OSX as my desktop
 and just run OpenBSD inside a VirtualBox...
 
 ...I sat down and spent way too much time fixing stuff
 in areas I'm totally unfamiliar with.
 
 Anyhow, porting this over fixes this bug for me:
 
 https://bugs.freedesktop.org//attachment.cgi?id=41531
 
 
 Index: i915_drv.c
 ===================================================================
 RCS file: /cvs/src/sys/dev/pci/drm/i915_drv.c,v
 retrieving revision 1.101
 diff -p -u -r1.101 i915_drv.c
 --- i915_drv.c 21 Sep 2010 23:05:41 -0000      1.101
 +++ i915_drv.c 29 Jan 2011 00:05:05 -0000
 @@ -995,17 +995,19 @@ inteldrm_chipset_flush(struct inteldrm_s
                bus_space_write_4(dev_priv->ifp.i9xx.bst,
                    dev_priv->ifp.i9xx.bsh, 0, 1);
        } else {
 -              /*
 -               * I8XX don't have a flush page mechanism, but do have the
 -               * cache. Do it the bruteforce way. we write 1024 byes into
 -               * the cache, then clflush them out so they'll kick the stuff
 -               * we care about out of the chipset cache.
 -               */
 -              if (dev_priv->ifp.i8xx.kva != NULL) {
 -                      memset(dev_priv->ifp.i8xx.kva, 0, 1024);
 -                      agp_flush_cache_range((vaddr_t)dev_priv->ifp.i8xx.kva,
 -                          1024);
 +              int i;
 +
 +              wbinvd();
 +
 +#define I830_HIC        0x70
 +
 +              I915_WRITE(I830_HIC, (I915_READ(I830_HIC) | (1<<31)));
 +              for (i = 1000; i; i--) {
 +                      if (!(I915_READ(I830_HIC) & (1<<31)))
 +                              break;
 +                      delay(100);
                }
 +
        }
  }

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