On Thu, May 19, 2011 at 01:37:15PM +0200, Mark Kettenis wrote:
> Spontanious detach usually is related to issues with Active State
> Power Management (ASPM).  Indeed it seems there is an errata for the
> Intel 82573 that affects the 82574 as well.
> 
> I don't have time to write a diff for this right now.  But perhaps
> somebody else can pick this up.

Could you try this?
 
Index: if_em.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_em.c,v
retrieving revision 1.256
diff -p -u -p -u -r1.256 if_em.c
--- if_em.c     22 Apr 2011 10:09:57 -0000      1.256
+++ if_em.c     19 May 2011 09:59:43 -0000
@@ -2619,13 +2619,6 @@ em_initialize_receive_unit(struct em_sof
                E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum);
        }
 
-       /*
-        * XXX TEMPORARY WORKAROUND: on some systems with 82573
-        * long latencies are observed, like Lenovo X60.
-        */
-       if (sc->hw.mac_type == em_82573)
-               E1000_WRITE_REG(&sc->hw, RDTR, 0x20);
-
        /* Enable Receives */
        E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
 
Index: if_em_hw.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_em_hw.c,v
retrieving revision 1.65
diff -p -u -p -u -r1.65 if_em_hw.c
--- if_em_hw.c  2 May 2011 18:16:58 -0000       1.65
+++ if_em_hw.c  19 May 2011 09:58:05 -0000
@@ -1343,6 +1343,19 @@ em_init_hw(struct em_hw *hw)
                gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
                E1000_WRITE_REG(hw, GCR, gcr);
        }
+       if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
+               uint16_t apsm_reg;
+               int cap_off;
+               struct pci_attach_args *pa = &((struct em_osdep 
*)hw->back)->em_pa;
+
+               if (pci_get_capability(pa->pa_pc, pa->pa_tag,
+                   PCI_CAP_PCIEXPRESS, &cap_off, NULL) != 0) {
+                       em_read_pci_cfg(hw, cap_off + PCI_PCIE_LCSR, &apsm_reg);
+                       printf("ASPM 0x%x -> 0x%x\n", apsm_reg, apsm_reg & 
~PCI_PCIE_LCSR_ASPM_L1);
+                       apsm_reg &= ~PCI_PCIE_LCSR_ASPM_L1;
+                       em_write_pci_cfg(hw, cap_off + PCI_PCIE_LCSR, 
&apsm_reg);
+               }
+       }
        /*
         * Clear all of the statistics registers (clear on read).  It is
         * important that we do this after we have tried to establish link

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