On Fri, Mar 11, 2016 at 08:08:14PM +0100, Martin Pieuchot wrote:
> But taking a step back, why is the SMBALERT firing constantly on your
> system, what does that mean? If it is always on when you have a USB
> interrupt then this really smells like the symptom of something else.
>
> But if we're always ignoring this condition then why don't we mask it
> in hardware?
Below is a full trace that shows what I'm seeing with the debug diff also
shown below. The trace is quite long but just scroll through it all to get
the full picture.
Note that I've verified that, during boot, ichiic_intr() is always being
called from ichiic_i2c_exec() in polling mode, not directly from interrupt.
So either the SMB alert is some side effect of spdmem0 i2c bus probes,
or the bit is always set no matter what.
Without the diff the ehci problem is seen between these lines, when
ehci (uhub0) starts scanning the USB bus:
spkr0 at pcppi0
uhub1 at uhub0 port 1 "Intel product 0x07db" rev 2.00/0.02 addr 2
As far as I understand what Theo explained to me, the current theory is that
the ehci interrupt handler never gets to run because, on this machine, ehci
is after ichiic in the list of interrupt handlers and the ichiic SMBALERT
interrupt bit gets set during spdmem probes (for an unknown reason, so it's
unclear how to prevent this from happening in hardware).
The bit then never gets cleared, but ichiic_intr still looks at it and sees
it as being set when a shared interrupt with ehci occurs, and claims the
interrupt. So ichiic ends up claiming interrupts that were meant for ehci,
after spdmem is done and when ehci starts doing work.
The proposed diff works around the issue by ignoring the SMBALERT bit in
ichiic. It also acks interrupts ("clear status bits") before checking status
bits for an early "not for us" exit, in an attempt to ensure we always tell
the ICH chip's interrupt logic to proceed (suggestion from Theo).
I have tried this second change in isolation and it doesn't fix the issue,
so writing status bits doesn't actually clear the ALERT.
However, the first change in isolation makes the system boot:
Index: ichiic.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/ichiic.c,v
retrieving revision 1.37
diff -u -p -r1.37 ichiic.c
--- ichiic.c 7 Dec 2015 02:56:36 -0000 1.37
+++ ichiic.c 12 Mar 2016 10:51:05 -0000
@@ -342,7 +342,7 @@ ichiic_intr(void *arg)
st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS);
if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR |
ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED |
- ICH_SMB_HS_SMBAL | ICH_SMB_HS_BDONE)) == 0)
+ ICH_SMB_HS_BDONE)) == 0)
/* Interrupt was not for us */
return (0);
If I run the following diff, I see this output on every ehci interrupt:
ichiic0: intr st 0x60<SMBAL,INUSE>
Index: ichiic.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/ichiic.c,v
retrieving revision 1.37
diff -u -p -r1.37 ichiic.c
--- ichiic.c 7 Dec 2015 02:56:36 -0000 1.37
+++ ichiic.c 12 Mar 2016 11:06:49 -0000
@@ -340,9 +340,11 @@ ichiic_intr(void *arg)
/* Read status */
st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS);
+ printf("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st,
+ ICH_SMB_HS_BITS);
if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR |
ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED |
- ICH_SMB_HS_SMBAL | ICH_SMB_HS_BDONE)) == 0)
+ ICH_SMB_HS_BDONE)) == 0)
/* Interrupt was not for us */
return (0);
The problem is that if we ignore real ichiic SMBALERT interrupts we might
do the wrong thing in other cases as kettenis explained.
However, I'd rather not try to implement proper handling for SMBALERT
interrupts on this machine since it seems I'm not actually seeing any
real SMBALERT interrupts. As stated earlier, it's possible to wire
SMBALERT to a GPIO on this board, so SMBALERT could mean anything here.
Any other ideas I could try? Or should I go ahead with these changes (with
an XXX comment as suggested by kettenis) and we wait for reports where
something else blows up because an SMBALERT interrupt is not being handled
properly? At present, we don't have any to code handle them anyway, and
FreeBSD also ignores them.
Index: ichiic.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/ichiic.c,v
retrieving revision 1.37
diff -u -p -r1.37 ichiic.c
--- ichiic.c 7 Dec 2015 02:56:36 -0000 1.37
+++ ichiic.c 11 Mar 2016 17:03:43 -0000
@@ -340,17 +340,18 @@ ichiic_intr(void *arg)
/* Read status */
st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS);
+
+ /* Clear status bits */
+ bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st);
+
if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR |
ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED |
- ICH_SMB_HS_SMBAL | ICH_SMB_HS_BDONE)) == 0)
+ ICH_SMB_HS_BDONE)) == 0)
/* Interrupt was not for us */
return (0);
- DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st,
- ICH_SMB_HS_BITS));
-
- /* Clear status bits */
- bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st);
+ printf("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st,
+ ICH_SMB_HS_BITS);
/* Check for errors */
if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) {
boot> boot bsd.test
booting hd0a:bsd.test: 6879236+2173872+267272+0+647168
[72+577224+384227]=0xa6de78
entry point at 0x1001000 [7205c766, 34000004, 24448b12, f060a304]
[ using 962168 bytes of bsd ELF symbol table ]
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
Copyright (c) 1995-2016 OpenBSD. All rights reserved. http://www.OpenBSD.org
OpenBSD 5.9-current (GENERIC.MP) #296: Fri Mar 11 18:03:52 CET 2016
[email protected]:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 8568823808 (8171MB)
avail mem = 8304930816 (7920MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 2.7 @ 0x7fbf0420 (7 entries)
bios0: vendor coreboot version "ADI_RCCVE-01.00.00.03-nodebug" date 03/14/2015
bios0: ADI Engineering RCC-VE
acpi0 at bios0: rev 2
acpi0: sleep states S0 S4 S5
acpi0: tables DSDT FACP SPCR HPET APIC MCFG SSDT
acpi0: wakeup devices EHC1(S4)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpihpet0 at acpi0: 14318179 Hz
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Atom(TM) CPU C2558 @ 2.40GHz, 1200.22 MHz
cpu0:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,MOVBE,POPCNT,DEADLINE,AES,RDRAND,NXE,LONG,LAHF,3DNOWP,PERF,ITSC,SMEP,ERMS,SENSOR,ARAT
cpu0: 1MB 64b/line 16-way L2 cache
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges
cpu0: apic clock running at 100MHz
cpu0: mwait min=64, max=64, C-substates=0.2.0.0.0.0.3, IBE
cpu1 at mainbus0: apid 2 (application processor)
cpu1: Intel(R) Atom(TM) CPU C2558 @ 2.40GHz, 1200.00 MHz
cpu1:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,MOVBE,POPCNT,DEADLINE,AES,RDRAND,NXE,LONG,LAHF,3DNOWP,PERF,ITSC,SMEP,ERMS,SENSOR,ARAT
cpu1: 1MB 64b/line 16-way L2 cache
cpu1: smt 0, core 1, package 0
cpu2 at mainbus0: apid 4 (application processor)
cpu2: Intel(R) Atom(TM) CPU C2558 @ 2.40GHz, 1200.00 MHz
cpu2:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,MOVBE,POPCNT,DEADLINE,AES,RDRAND,NXE,LONG,LAHF,3DNOWP,PERF,ITSC,SMEP,ERMS,SENSOR,ARAT
cpu2: 1MB 64b/line 16-way L2 cache
cpu2: smt 0, core 2, package 0
cpu3 at mainbus0: apid 6 (application processor)
cpu3: Intel(R) Atom(TM) CPU C2558 @ 2.40GHz, 1200.00 MHz
cpu3:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,MOVBE,POPCNT,DEADLINE,AES,RDRAND,NXE,LONG,LAHF,3DNOWP,PERF,ITSC,SMEP,ERMS,SENSOR,ARAT
cpu3: 1MB 64b/line 16-way L2 cache
cpu3: smt 0, core 3, package 0
ioapic0 at mainbus0: apid 2 pa 0xfec00000, version 20, 24 pins
acpimcfg0 at acpi0 addr 0xe0000000, bus 0-255
acpiprt0 at acpi0: bus 1 (RP01)
acpiprt1 at acpi0: bus 2 (RP02)
acpiprt2 at acpi0: bus 3 (RP03)
acpiprt3 at acpi0: bus 4 (RP04)
acpiprt4 at acpi0: bus 0 (PCI0)
acpicpu0 at acpi0: C1(@1 halt!), PSS
acpicpu1 at acpi0: C1(@1 halt!), PSS
acpicpu2 at acpi0: C1(@1 halt!), PSS
acpicpu3 at acpi0: C1(@1 halt!), PSS
cpu0: Enhanced SpeedStep 1200 MHz: speeds: 2400, 2200, 2000, 1800, 1600, 1400,
1200 MHz
pci0 at mainbus0 bus 0
pchb0 at pci0 dev 0 function 0 "Intel Atom C2000 Host" rev 0x02
ppb0 at pci0 dev 1 function 0 "Intel Atom C2000 PCIE" rev 0x02: msi
pci1 at ppb0 bus 1
ppb1 at pci0 dev 2 function 0 "Intel Atom C2000 PCIE" rev 0x02: msi
pci2 at ppb1 bus 2
ppb2 at pci0 dev 3 function 0 "Intel Atom C2000 PCIE" rev 0x02: msi
pci3 at ppb2 bus 3
em0 at pci3 dev 0 function 0 "Intel I211" rev 0x03: msi, address
00:08:a2:09:35:1c
ppb3 at pci0 dev 4 function 0 "Intel Atom C2000 PCIE" rev 0x02: msi
pci4 at ppb3 bus 4
em1 at pci4 dev 0 function 0 "Intel I211" rev 0x03: msi, address
00:08:a2:09:35:1d
vendor "Intel", unknown product 0x1f18 (class processor subclass Co-processor,
rev 0x02) at pci0 dev 11 function 0 not configured
pchb1 at pci0 dev 14 function 0 "Intel Atom C2000 RAS" rev 0x02
"Intel Atom C2000 RCEC" rev 0x02 at pci0 dev 15 function 0 not configured
"Intel Atom C2000 SMBus" rev 0x02 at pci0 dev 19 function 0 not configured
em2 at pci0 dev 20 function 0 "Intel I354 SGMII" rev 0x03: msi, address
00:08:a2:09:35:18
em3 at pci0 dev 20 function 1 "Intel I354 SGMII" rev 0x03: msi, address
00:08:a2:09:35:19
em4 at pci0 dev 20 function 2 "Intel I354 SGMII" rev 0x03: msi, address
00:08:a2:09:35:1a
em5 at pci0 dev 20 function 3 "Intel I354 SGMII" rev 0x03: msi, address
00:08:a2:09:35:1b
ehci0 at pci0 dev 22 function 0 "Intel Atom C2000 USB" rev 0x02: apic 2 int 22
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "Intel EHCI root hub" rev 2.00/1.00 addr 1
ahci0 at pci0 dev 23 function 0 "Intel Atom C2000 AHCI" rev 0x02: msi, AHCI 1.3
scsibus1 at ahci0: 32 targets
ahci1 at pci0 dev 24 function 0 "Intel Atom C2000 AHCI" rev 0x02: msi, AHCI 1.3
scsibus2 at ahci1: 32 targets
pcib0 at pci0 dev 31 function 0 "Intel Atom C2000 PCU" rev 0x02
ichiic0 at pci0 dev 31 function 3 "Intel Atom C2000 PCU SMBus" rev 0x02: apic 2
int 22
iic0 at ichiic0
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
iic0: addr 0x2e 00=3d wordsichiic0: intr st 0x62<INTR,SMBAL,INUSE>
00=3d3dichiic0: intr st 0x62<INTR,SMBAL,INUSE>
01=0000ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
02=0000ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
03=0000ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
04=0000ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
05=0000ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
06=0000ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
07=0000
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
iic0: addr 0x2f 00=25 01=a0 02=23 03=60 04=23 05=e0 06=2b 07=e0 0a=5c 10=80
13=1d 14=1f 15=1f 16=1f 17=07 18=12 19=64 1a=64 1b=64 1c=64 1d=64 21=0e 23=08
27=85 2b=0f 30=55 31=55 32=55 33=55 34=55ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
35=ffichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
40=ff 41=01 42=2b 43=38 44=01 45=2a 46=19 47=10 48=66 49=f5 4c=f8ichiic0: intr
st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
4d=ffichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
4e=ff 4f=f0 51=fb 52=7f 53=7f 54=7f 55=7f 56=e6 57=7f 58=7f 59=7f 5a=7f 5b=d1
5c=7f 5d=7f 5e=7f 5f=7f 60=bc 61=7f 62=7f 63=7f 64=7f 65=a7 66=7f 67=7f 68=7f
69=7f 6a=92 6b=7f 6c=7f 6d=7f 6e=7f 6f=92 70=7f 71=7f 72=7f 73=7f 74=92 75=7f
76=7f 77=7f 78=7f 79=0a 7a=c0ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
80=ff 81=01 82=2b 83=38 84=01 85=2a 86=19 87=10 88=66 89=f5 8c=f8ichiic0: intr
st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
8d=ffichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
8e=ff 8f=f0 91=fb 92=7f 93=7f 94=7f 95=7f 96=e6 97=7f 98=7f 99=7f 9a=7f 9b=d1
9c=7f 9d=7f 9e=7f 9f=7f a0=bc a1=7f a2=7f a3=7f a4=7f a5=a7 a6=7f a7=7f a8=7f
a9=7f aa=92 ab=7f ac=7f ad=7f ae=7f af=92 b0=7f b1=7f b2=7f b3=7f b4=92 b5=7f
b6=7f b7=7f b8=7f b9=0a ba=c0 c4=63 c5=80 c8=a2 ca=36 cb=12 cc=1e cd=0a ce=04
cf=41 d0=20 d3=07 d4=20 d6=20 d7=40 e0=81 e3=07 fc=02 fd=1d fe=5d ff=02
wordsichiic0: intr st 0x62<INTR,SMBAL,INUSE>
00=25ffichiic0: intr st 0x62<INTR,SMBAL,INUSE>
01=80ffichiic0: intr st 0x62<INTR,SMBAL,INUSE>
02=23ffichiic0: intr st 0x62<INTR,SMBAL,INUSE>
03=60ffichiic0: intr st 0x62<INTR,SMBAL,INUSE>
04=23ffichiic0: intr st 0x62<INTR,SMBAL,INUSE>
05=c0ffichiic0: intr st 0x62<INTR,SMBAL,INUSE>
06=2cffichiic0: intr st 0x62<INTR,SMBAL,INUSE>
07=00ff
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
spdmem0 at iic0 addr 0x50:ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
ichiic0: intr st 0x62<INTR,SMBAL,INUSE>
8GB DDR3 SDRAM PC3-14200
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
ichiic0: intr st 0x64<DEVERR,SMBAL,INUSE>
isa0 at pcib0
isadma0 at isa0
com0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo
com1 at isa0 port 0x2f8/8 irq 3: ns16550a, 16 byte fifo
com1: console
pcppi0 at isa0 port 0x61
spkr0 at pcppi0
uhub1 at uhub0 port 1 "Intel product 0x07db" rev 2.00/0.02 addr 2
umass0 at uhub1 port 4 configuration 1 interface 0 "Generic Ultra Fast Media"
rev 2.00/1.98 addr 3
umass0: using SCSI over Bulk-Only
scsibus3 at umass0: 2 targets, initiator 0
sd0 at scsibus3 targ 1 lun 0: <Generic, Ultra HS-COMBO, 1.98> SCSI0 0/direct
removable serial.04242240000000225001
sd0: 3776MB, 512 bytes/sector, 7733248 sectors
vscsi0 at root
scsibus4 at vscsi0: 256 targets
softraid0 at root
scsibus5 at softraid0: 256 targets
root on sd0a (9937347707aff99b.a) swap on sd0b dump on sd0b
