On Sat, Sep 16, 2017 at 02:07:47PM +0200, Matthieu Herrb wrote:
> On Sat, Sep 16, 2017 at 06:57:38PM +1000, Jonathan Gray wrote:
> > On Sat, Sep 16, 2017 at 10:03:58AM +0200, matth...@herrb.eu wrote:
> > > >Synopsis: no CPU frequency scaling on Purism Librem 13v2
> > > >Category: kern/amd64
> > > >Environment:
> > > System : OpenBSD 6.2
> > > Details : OpenBSD 6.2-beta (GENERIC.MP) #0: Fri Sep 15 23:36:30
> > > CEST 2017
> > > matth...@librem.herrb.net:/usr/obj/GENERIC.MP
> > >
> > > Architecture: OpenBSD.amd64
> > > Machine : amd64
> > > >Description:
> > > There is no hw.setperf sysctl available to control the CPU speed
> > >
> > > >How-To-Repeat:
> > > Try to use apmd -A to save some battery life
> > > >Fix:
> > > unknown
> >
> > If vendor supplied acpi tables neglect to include _PSS in the aml you
> > won't get different cpu speed states on anything more recent than
> > a pentium m.
> >
> Hi,
>
> On PureOS (the Debian derivative shipped by Purism) it's the
> intel_pstate driver that is used to control the CPU core speeds.
>
> Should I try to ask Purism to provide the proper _PSS objects in
> their BIOS, or is there hope to get P states support at some point?
Given there is no _PSS or _CPC the alternative seems to be MSRs.
The ones related to hardware p states (HWP) available in broadwell
and later.
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20170303 (64-bit version)
* Copyright (c) 2000 - 2017 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
* Disassembly of SSDT.3, Sat Sep 16 23:19:18 2017
*
* Original Table Header:
* Signature "SSDT"
* Length 0x00000308 (776)
* Revision 0x02
* Checksum 0xEF
* OEM ID "CORE "
* OEM Table ID "COREBOOT"
* OEM Revision 0x0000002A (42)
* Compiler ID "CORE"
* Compiler Version 0x0000002A (42)
*/
DefinitionBlock ("", "SSDT", 2, "CORE ", "COREBOOT", 0x0000002A)
{
Device (CTBL)
{
Name (_HID, "BOOT0000") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadOnly,
0x7AB8F000, // Address Base
0x00008000, // Address Length
)
})
}
Processor (\_PR.CP00, 0x00, 0x00001800, 0x06)
{
Name (_CST, Package (0x04) // _CST: C-States
{
0x00000003,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000001, // Address
0x01, // Access Size
)
},
0x00000001,
0x00000000,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x00000002,
0x0000004F,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000033, // Address
0x01, // Access Size
)
},
0x00000003,
0x00000097,
0x000000C8
}
})
}
Processor (\_PR.CP01, 0x01, 0x00000000, 0x00)
{
Name (_CST, Package (0x04) // _CST: C-States
{
0x00000003,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000001, // Address
0x01, // Access Size
)
},
0x00000001,
0x00000000,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x00000002,
0x0000004F,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000033, // Address
0x01, // Access Size
)
},
0x00000003,
0x00000097,
0x000000C8
}
})
}
Processor (\_PR.CP02, 0x02, 0x00000000, 0x00)
{
Name (_CST, Package (0x04) // _CST: C-States
{
0x00000003,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000001, // Address
0x01, // Access Size
)
},
0x00000001,
0x00000000,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x00000002,
0x0000004F,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000033, // Address
0x01, // Access Size
)
},
0x00000003,
0x00000097,
0x000000C8
}
})
}
Processor (\_PR.CP03, 0x03, 0x00000000, 0x00)
{
Name (_CST, Package (0x04) // _CST: C-States
{
0x00000003,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000001, // Address
0x01, // Access Size
)
},
0x00000001,
0x00000000,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x00000002,
0x0000004F,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000033, // Address
0x01, // Access Size
)
},
0x00000003,
0x00000097,
0x000000C8
}
})
}
}
