On Thu, Oct 25, 2018 at 08:12:13PM +0200, Mark Kettenis wrote: > Found the issue. The kernel advertises support for the I915_MMAP_WC > option, but we don't actually implement that functonality correctly > :(. As a result we create a cachable mapping instead of a > write-combining (uncached) one. On hardware generations that aren't > cache coherent this means that the hardware may see stale memory > contents. So the GPU starts executing some random garbage which is > very likely to result in a hang. > > The diff below stops advertising I915_MMAP_WC support. This is a > workaround. I'm looking into implementing I915_MMAP_WC properly, but > that may require a bit of uvm surgery. > > Mike, it is likely this will fix your "sparkle" issue as well. > > Cheers, > > Mark >
I have applied this and don't see the sparkle effect anymore. Sometimes it took a while to show up, so I'll keep an eye on it and let you know. -ml > > Index: dev/pci/drm/i915/i915_dma.c > =================================================================== > RCS file: /cvs/src/sys/dev/pci/drm/i915/i915_dma.c,v > retrieving revision 1.26 > diff -u -p -r1.26 i915_dma.c > --- dev/pci/drm/i915/i915_dma.c 30 Sep 2017 07:36:56 -0000 1.26 > +++ dev/pci/drm/i915/i915_dma.c 25 Oct 2018 18:01:59 -0000 > @@ -156,9 +156,11 @@ static int i915_getparam(struct drm_devi > case I915_PARAM_HAS_COHERENT_PHYS_GTT: > value = 1; > break; > +#ifdef notyet > case I915_PARAM_MMAP_VERSION: > value = 1; > break; > +#endif > case I915_PARAM_SUBSLICE_TOTAL: > value = INTEL_INFO(dev)->subslice_total; > if (!value)
