On Wed, Oct 16, 2019 at 10:42:45AM +0200, Sebastien Marie wrote:
> On Wed, Oct 16, 2019 at 09:16:41AM +0200, Sebastien Marie wrote:
>
> > uvm_fault(0xffffffff82011010, 0x18, 0, 1) -> e
> > kernel: page fault trap, code=0
> > Stopped at dc_link_aux_transfer+0x85: movq 0x18(%r14),%rax
> > ddb{0}> trace
> > dc_link_aux_transfer(ffff80000013c400,0,ffffffff822db9ad,ffffffff822dbb30,1,0)
> > at dc_link_aux_transfer+0x85
> > dm_dp_aux_transfer(ffff800000a838a0,ffffffff822db9a8) at
> > dm_dp_aux_transfer+0xdc
> > drm_dp_dpcd_access(ffff800000a838a0,9,0,ffffffff822dbb30,1) at
> > drm_dp_dpcd_access+0x8d
> > drm_dp_dpcd_read(ffff800000a838a0,0,ffffffff822dbb30,10) at
> > drm_dp_dpcd_read+0x45
> > dm_helpers_dp_read_dpcd(ffff800000a33000,ffff800000a79800,0,ffffffff822dbb30,10)
> > at dm_helpers_dp_read_dpcd+0x43
> > core_link_read_dpcd(ffff800000a79800,0,ffffffff822dbb30,10) at
> > core_link_read_dpcd+0x2d
> > retrieve_link_cap(ffff800000a79800) at retrieve_link_cap+0x40
> > dc_link_detect(ffff800000a79800,0) at dc_link_detect+0x99e
> > dm_hw_init(ffff80000036d000) at dm_hw_init+0xa96
> > amdgpu_device_init(ffff80000036d000,ffff80000037b000,ffff80000037b018,20016)
> > at amdgpu_device_init+0x1159
> > amdgpu_attachhook(ffff80000036d000) at amdgpu_attachhook+0x3b
> > config_process_deferred_mountroot() at
> > config_process_deferred_mountroot+0x6b
> > main(0) at main+0x745
> > end trace frame: 0x0, count: -13
>
> it fails in dc_link_aux_transfer() function, when calling
> aux_engine->funcs->acquire(aux_engine, ddc_pin)
> because aux_engine is 0x0.
Try the following, adapted from this linux commit
commit 0e8e4fbf8d8905071c045f2922de55adbe1a6abe
Author: Hersen Wu <[email protected]>
Date: Tue Aug 21 09:35:47 2018 -0400
drm/amd/display: num of sw i2c/aux engines less than num of connectors
[why]
AMD Stoney reference board, there are only 2 pipes (not include
underlay), and 3 connectors. resource creation, only
2 I2C/AUX engines are created. Within dc_link_aux_transfer, when
pin_data_en =2, refer to enengines[ddc_pin->pin_data->en] = NULL.
NULL point is referred later causing system crash.
[how]
each asic design has fixed number of ddc engines at hw side.
for each ddc engine, create its i2x/aux engine at sw side.
Signed-off-by: Hersen Wu <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Index: sys/dev/pci/drm/amd/display/dc/dce100/dce100_resource.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/amd/display/dc/dce100/dce100_resource.c,v
retrieving revision 1.1
diff -u -p -r1.1 dce100_resource.c
--- sys/dev/pci/drm/amd/display/dc/dce100/dce100_resource.c 21 May 2019
22:40:08 -0000 1.1
+++ sys/dev/pci/drm/amd/display/dc/dce100/dce100_resource.c 16 Oct 2019
09:50:00 -0000
@@ -371,7 +371,8 @@ static const struct resource_caps res_ca
.num_timing_generator = 6,
.num_audio = 6,
.num_stream_encoder = 6,
- .num_pll = 3
+ .num_pll = 3,
+ .num_ddc = 6,
};
#define CTX ctx
@@ -963,6 +964,9 @@ static bool construct(
"DC: failed to create output pixel
processor!\n");
goto res_create_fail;
}
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
Index: sys/dev/pci/drm/amd/display/dc/dce110/dce110_resource.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/amd/display/dc/dce110/dce110_resource.c,v
retrieving revision 1.1
diff -u -p -r1.1 dce110_resource.c
--- sys/dev/pci/drm/amd/display/dc/dce110/dce110_resource.c 21 May 2019
22:40:08 -0000 1.1
+++ sys/dev/pci/drm/amd/display/dc/dce110/dce110_resource.c 16 Oct 2019
09:50:00 -0000
@@ -377,6 +377,7 @@ static const struct resource_caps carriz
.num_audio = 3,
.num_stream_encoder = 3,
.num_pll = 2,
+ .num_ddc = 3,
};
static const struct resource_caps stoney_resource_cap = {
@@ -385,6 +386,7 @@ static const struct resource_caps stoney
.num_audio = 3,
.num_stream_encoder = 3,
.num_pll = 2,
+ .num_ddc = 3,
};
#define CTX ctx
@@ -1295,7 +1297,9 @@ static bool construct(
"DC: failed to create output pixel
processor!\n");
goto res_create_fail;
}
+ }
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
Index: sys/dev/pci/drm/amd/display/dc/dce112/dce112_resource.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/amd/display/dc/dce112/dce112_resource.c,v
retrieving revision 1.1
diff -u -p -r1.1 dce112_resource.c
--- sys/dev/pci/drm/amd/display/dc/dce112/dce112_resource.c 21 May 2019
22:40:08 -0000 1.1
+++ sys/dev/pci/drm/amd/display/dc/dce112/dce112_resource.c 16 Oct 2019
09:50:00 -0000
@@ -383,6 +383,7 @@ static const struct resource_caps polari
.num_audio = 6,
.num_stream_encoder = 6,
.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
+ .num_ddc = 6,
};
static const struct resource_caps polaris_11_resource_cap = {
@@ -390,6 +391,7 @@ static const struct resource_caps polari
.num_audio = 5,
.num_stream_encoder = 5,
.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
+ .num_ddc = 5,
};
#define CTX ctx
@@ -1245,6 +1247,9 @@ static bool construct(
"DC:failed to create output pixel
processor!\n");
goto res_create_fail;
}
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
Index: sys/dev/pci/drm/amd/display/dc/dce120/dce120_resource.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/amd/display/dc/dce120/dce120_resource.c,v
retrieving revision 1.1
diff -u -p -r1.1 dce120_resource.c
--- sys/dev/pci/drm/amd/display/dc/dce120/dce120_resource.c 21 May 2019
22:40:08 -0000 1.1
+++ sys/dev/pci/drm/amd/display/dc/dce120/dce120_resource.c 16 Oct 2019
09:55:39 -0000
@@ -402,6 +402,7 @@ static const struct resource_caps res_ca
.num_audio = 7,
.num_stream_encoder = 6,
.num_pll = 6,
+ .num_ddc = 6,
};
static const struct dc_debug_options debug_defaults = {
@@ -1020,6 +1021,12 @@ static bool construct(
dm_error(
"DC: failed to create output pixel
processor!\n");
}
+
+ /* check next valid pipe */
+ j++;
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -1027,9 +1034,6 @@ static bool construct(
"DC:failed to create aux
engine!!\n");
goto res_create_fail;
}
-
- /* check next valid pipe */
- j++;
}
/* valid pipe num */
Index: sys/dev/pci/drm/amd/display/dc/dce80/dce80_resource.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/amd/display/dc/dce80/dce80_resource.c,v
retrieving revision 1.1
diff -u -p -r1.1 dce80_resource.c
--- sys/dev/pci/drm/amd/display/dc/dce80/dce80_resource.c 21 May 2019
22:40:08 -0000 1.1
+++ sys/dev/pci/drm/amd/display/dc/dce80/dce80_resource.c 16 Oct 2019
10:05:05 -0000
@@ -366,6 +366,7 @@ static const struct resource_caps res_ca
.num_audio = 6,
.num_stream_encoder = 6,
.num_pll = 3,
+ .num_ddc = 6,
};
static const struct resource_caps res_cap_81 = {
@@ -373,6 +374,7 @@ static const struct resource_caps res_ca
.num_audio = 7,
.num_stream_encoder = 7,
.num_pll = 3,
+ .num_ddc = 6,
};
static const struct resource_caps res_cap_83 = {
@@ -380,6 +382,7 @@ static const struct resource_caps res_ca
.num_audio = 6,
.num_stream_encoder = 6,
.num_pll = 2,
+ .num_ddc = 2,
};
static const struct dce_dmcu_registers dmcu_regs = {
@@ -935,7 +938,9 @@ static bool dce80_construct(
dm_error("DC: failed to create output pixel
processor!\n");
goto res_create_fail;
}
+ }
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -1131,6 +1136,16 @@ static bool dce81_construct(
}
}
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC:failed to create aux engine!!\n");
+ goto res_create_fail;
+ }
+ }
+
dc->caps.max_planes = pool->base.pipe_count;
dc->caps.disable_dp_clk_share = true;
@@ -1309,6 +1324,16 @@ static bool dce83_construct(
if (pool->base.opps[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error("DC: failed to create output pixel
processor!\n");
+ goto res_create_fail;
+ }
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC:failed to create aux engine!!\n");
goto res_create_fail;
}
}
Index: sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_resource.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_resource.c,v
retrieving revision 1.1
diff -u -p -r1.1 dcn10_resource.c
--- sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_resource.c 21 May 2019
22:40:08 -0000 1.1
+++ sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_resource.c 16 Oct 2019
09:54:49 -0000
@@ -500,6 +500,7 @@ static const struct resource_caps res_ca
.num_audio = 4,
.num_stream_encoder = 4,
.num_pll = 4,
+ .num_ddc = 4,
};
static const struct dc_debug_options debug_defaults_drv = {
@@ -1292,7 +1293,11 @@ static bool construct(
dm_error("DC: failed to create tg!\n");
goto fail;
}
+ /* check next valid pipe */
+ j++;
+ }
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -1300,9 +1305,6 @@ static bool construct(
"DC:failed to create aux engine!!\n");
goto fail;
}
-
- /* check next valid pipe */
- j++;
}
/* valid pipe num */
Index: sys/dev/pci/drm/amd/display/dc/inc/resource.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/amd/display/dc/inc/resource.h,v
retrieving revision 1.1
diff -u -p -r1.1 resource.h
--- sys/dev/pci/drm/amd/display/dc/inc/resource.h 21 May 2019 22:40:09
-0000 1.1
+++ sys/dev/pci/drm/amd/display/dc/inc/resource.h 16 Oct 2019 09:50:00
-0000
@@ -44,6 +44,7 @@ struct resource_caps {
int num_stream_encoder;
int num_pll;
int num_dwb;
+ int num_ddc;
};
struct resource_straps {
