On Wed, Jul 07, 2021 at 11:02:27AM -0400, Josh Rickmar wrote:
> With latest amd64 snapshot on my Thinkpad E485 I'm only seeing a
> black screen when using X. xenodm is still running, and with some
> finger memory I can still log in and run various X applications, but
> none of it is visible.
>
> dmesg (note the drm and framebuffer errors at the end):
> OpenBSD 6.9-current (GENERIC.MP) #111: Tue Jul 6 22:56:50 MDT 2021
> [email protected]:/usr/src/sys/arch/amd64/compile/GENERIC.MP
> real mem = 16762552320 (15986MB)
> avail mem = 16238493696 (15486MB)
> random: good seed from bootblocks
> mpath0 at root
> scsibus0 at mpath0: 256 targets
> mainbus0 at root
> bios0 at mainbus0: SMBIOS rev. 3.1 @ 0x986eb000 (62 entries)
> bios0: vendor LENOVO version "R0UET78W (1.58 )" date 11/17/2020
> bios0: LENOVO 20KUCTO1WW
> acpi0 at bios0: ACPI 5.0
> acpi0: sleep states S0 S3 S4 S5
> acpi0: tables DSDT FACP SSDT SSDT CRAT CDIT SSDT TPM2 UEFI MSDM BATB HPET
> APIC MCFG SBST WSMT VFCT IVRS FPDT SSDT SSDT SSDT BGRT UEFI SSDT
> acpi0: wakeup devices GPP0(S3) GPP1(S3) GPP2(S3) GPP3(S3) GPP4(S3) GPP5(S3)
> GPP6(S3) GP17(S3) XHC0(S3) XHC1(S3) GP18(S3) LID_(S3) SLPB(S3)
> acpitimer0 at acpi0: 3579545 Hz, 32 bits
> acpihpet0 at acpi0: 14318180 Hz
> acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
> cpu0 at mainbus0: apid 0 (boot processor)
> cpu0: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.62 MHz, 17-11-00
> cpu0:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu0: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
> 64b/line 8-way L2 cache
> cpu0: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu0: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu0: smt 0, core 0, package 0
> mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges
> cpu0: apic clock running at 24MHz
> cpu0: mwait min=64, max=64, C-substates=1.1, IBE
> cpu1 at mainbus0: apid 1 (application processor)
> cpu1: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.26 MHz, 17-11-00
> cpu1:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu1: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
> 64b/line 8-way L2 cache
> cpu1: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu1: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu1: disabling user TSC (skew=-7211601250)
> cpu1: smt 1, core 0, package 0
> cpu2 at mainbus0: apid 2 (application processor)
> cpu2: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.26 MHz, 17-11-00
> cpu2:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu2: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
> 64b/line 8-way L2 cache
> cpu2: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu2: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu2: disabling user TSC (skew=-7211601210)
> cpu2: smt 0, core 1, package 0
> cpu3 at mainbus0: apid 3 (application processor)
> cpu3: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.26 MHz, 17-11-00
> cpu3:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu3: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
> 64b/line 8-way L2 cache
> cpu3: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu3: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu3: disabling user TSC (skew=-7211601260)
> cpu3: smt 1, core 1, package 0
> cpu4 at mainbus0: apid 4 (application processor)
> cpu4: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.26 MHz, 17-11-00
> cpu4:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu4: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
> 64b/line 8-way L2 cache
> cpu4: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu4: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu4: disabling user TSC (skew=-7211601230)
> cpu4: smt 0, core 2, package 0
> cpu5 at mainbus0: apid 5 (application processor)
> cpu5: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.26 MHz, 17-11-00
> cpu5:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu5: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
> 64b/line 8-way L2 cache
> cpu5: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu5: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu5: disabling user TSC (skew=-7211601260)
> cpu5: smt 1, core 2, package 0
> cpu6 at mainbus0: apid 6 (application processor)
> cpu6: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.26 MHz, 17-11-00
> cpu6:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu6: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
> 64b/line 8-way L2 cache
> cpu6: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu6: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu6: disabling user TSC (skew=-7211601200)
> cpu6: smt 0, core 3, package 0
> cpu7 at mainbus0: apid 7 (application processor)
> cpu7: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.26 MHz, 17-11-00
> cpu7:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu7: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
> 64b/line 8-way L2 cache
> cpu7: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu7: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
> cpu7: disabling user TSC (skew=-7211601250)
> cpu7: smt 1, core 3, package 0
> ioapic0 at mainbus0: apid 32 pa 0xfec00000, version 21, 24 pins, can't remap
> ioapic1 at mainbus0: apid 33 pa 0xfec01000, version 21, 32 pins, can't remap
> acpimcfg0 at acpi0
> acpimcfg0: addr 0xf8000000, bus 0-63
> acpiprt0 at acpi0: bus 0 (PCI0)
> acpiprt1 at acpi0: bus 1 (GPP0)
> acpiprt2 at acpi0: bus 2 (GPP1)
> acpiprt3 at acpi0: bus 3 (GPP2)
> acpiprt4 at acpi0: bus -1 (GPP3)
> acpiprt5 at acpi0: bus -1 (GPP4)
> acpiprt6 at acpi0: bus 4 (GPP5)
> acpiprt7 at acpi0: bus -1 (GPP6)
> acpiprt8 at acpi0: bus 5 (GP17)
> acpiprt9 at acpi0: bus 6 (GP18)
> acpiec0 at acpi0
> acpibtn0 at acpi0: PWRB
> acpipci0 at acpi0 PCI0: 0x00000010 0x00000011 0x00000000
> acpicmos0 at acpi0
> acpibat0 at acpi0: BAT0 model "01AV448" serial 2798 type LiP oem "Celxpert"
> acpiac0 at acpi0: AC unit online
> acpithinkpad0 at acpi0: version 2.0
> "SMB0001" at acpi0 not configured
> acpibtn1 at acpi0: LID_
> acpibtn2 at acpi0: SLPB
> "PNP0C14" at acpi0 not configured
> "PNP0C14" at acpi0 not configured
> "PNP0C14" at acpi0 not configured
> "STM7304" at acpi0 not configured
> "USBC000" at acpi0 not configured
> acpicpu0 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
> acpicpu1 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
> acpicpu2 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
> acpicpu3 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
> acpicpu4 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
> acpicpu5 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
> acpicpu6 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
> acpicpu7 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
> acpipwrres0 at acpi0: P0ST, resource for SATA
> acpipwrres1 at acpi0: P3ST, resource for SATA
> acpivideo0 at acpi0: VGA_
> acpivout0 at acpivideo0: LCD_
> cpu0: 1996 MHz: speeds: 2000 1700 1600 MHz
> pci0 at mainbus0 bus 0
> ksmn0 at pci0 dev 0 function 0 "AMD 17h/1xh Root Complex" rev 0x00
> "AMD 17h/1xh IOMMU" rev 0x00 at pci0 dev 0 function 2 not configured
> pchb0 at pci0 dev 1 function 0 "AMD 17h PCIE" rev 0x00
> ppb0 at pci0 dev 1 function 1 "AMD 17h/1xh PCIE" rev 0x00: msi
> pci1 at ppb0 bus 1
> ppb1 at pci0 dev 1 function 2 "AMD 17h/1xh PCIE" rev 0x00: msi
> pci2 at ppb1 bus 2
> re0 at pci2 dev 0 function 0 "Realtek 8168" rev 0x10: RTL8168GU/8111GU
> (0x5080), msi, address e8:6a:64:f0:f8:14
> rgephy0 at re0 phy 7: RTL8251 PHY, rev. 0
> ppb2 at pci0 dev 1 function 3 "AMD 17h/1xh PCIE" rev 0x00: msi
> pci3 at ppb2 bus 3
> sdhc0 at pci3 dev 0 function 0 "O2 Micro 0Z8621 SD/MMC" rev 0x01: apic 33 int
> 8
> sdhc0: SDHC 4.0, 50 MHz base clock
> sdmmc0 at sdhc0: 4-bit, sd high-speed, mmc high-speed, ddr52, dma
> ppb3 at pci0 dev 1 function 6 "AMD 17h/1xh PCIE" rev 0x00: msi
> pci4 at ppb3 bus 4
> iwm0 at pci4 dev 0 function 0 "Intel Dual Band Wireless-AC 8265" rev 0x78, msi
> pchb1 at pci0 dev 8 function 0 "AMD 17h PCIE" rev 0x00
> ppb4 at pci0 dev 8 function 1 "AMD 17h/1xh PCIE" rev 0x00
> pci5 at ppb4 bus 5
> amdgpu0 at pci5 dev 0 function 0 "ATI Radeon Vega" rev 0xc4
> drm0 at amdgpu0
> amdgpu0: msi
> azalia0 at pci5 dev 0 function 1 "ATI Radeon Vega HD Audio" rev 0x00: msi
> azalia0: no supported codecs
> ccp0 at pci5 dev 0 function 2 "AMD 17h/1xh Crypto" rev 0x00
> xhci0 at pci5 dev 0 function 3 "AMD 17h/1xh xHCI" rev 0x00: msi, xHCI 1.10
> usb0 at xhci0: USB revision 3.0
> uhub0 at usb0 configuration 1 interface 0 "AMD xHCI root hub" rev 3.00/1.00
> addr 1
> xhci1 at pci5 dev 0 function 4 "AMD 17h/1xh xHCI" rev 0x00: msi, xHCI 1.10
> usb1 at xhci1: USB revision 3.0
> uhub1 at usb1 configuration 1 interface 0 "AMD xHCI root hub" rev 3.00/1.00
> addr 1
> azalia1 at pci5 dev 0 function 6 "AMD 17h/1xh HD Audio" rev 0x00: apic 33 int
> 30
> azalia1: codecs: Conexant/0x5111
> audio0 at azalia1
> ppb5 at pci0 dev 8 function 2 "AMD 17h/1xh PCIE" rev 0x00
> pci6 at ppb5 bus 6
> ahci0 at pci6 dev 0 function 0 "AMD FCH AHCI" rev 0x61: msi, AHCI 1.3.1
> ahci0: port 0: 6.0Gb/s
> scsibus1 at ahci0: 32 targets
> sd0 at scsibus1 targ 0 lun 0: <ATA, CT500MX500SSD1, M3CR> naa.500a0751e13ebe2f
> sd0: 476940MB, 512 bytes/sector, 976773168 sectors, thin
> piixpm0 at pci0 dev 20 function 0 "AMD FCH SMBus" rev 0x61: SMI
> iic0 at piixpm0
> spdmem0 at iic0 addr 0x50: 8GB DDR4 SDRAM PC4-19200 SO-DIMM
> spdmem1 at iic0 addr 0x52: 8GB DDR4 SDRAM PC4-19200 SO-DIMM
> iic1 at piixpm0
> pcib0 at pci0 dev 20 function 3 "AMD FCH LPC" rev 0x51
> pchb2 at pci0 dev 24 function 0 "AMD 17h/1xh Data Fabric" rev 0x00
> pchb3 at pci0 dev 24 function 1 "AMD 17h/1xh Data Fabric" rev 0x00
> pchb4 at pci0 dev 24 function 2 "AMD 17h/1xh Data Fabric" rev 0x00
> pchb5 at pci0 dev 24 function 3 "AMD 17h/1xh Data Fabric" rev 0x00
> pchb6 at pci0 dev 24 function 4 "AMD 17h/1xh Data Fabric" rev 0x00
> pchb7 at pci0 dev 24 function 5 "AMD 17h/1xh Data Fabric" rev 0x00
> pchb8 at pci0 dev 24 function 6 "AMD 17h/1xh Data Fabric" rev 0x00
> pchb9 at pci0 dev 24 function 7 "AMD 17h/1xh Data Fabric" rev 0x00
> isa0 at pcib0
> isadma0 at isa0
> pckbc0 at isa0 port 0x60/5 irq 1 irq 12
> pckbd0 at pckbc0 (kbd slot)
> wskbd0 at pckbd0: console keyboard
> pms0 at pckbc0 (aux slot)
> wsmouse0 at pms0 mux 0
> wsmouse1 at pms0 mux 0
> pms0: Synaptics clickpad, firmware 8.16, 0x1e2b1 0x940300 0x373740 0xf020a3
> 0x12e800
> pcppi0 at isa0 port 0x61
> spkr0 at pcppi0
> vmm0 at mainbus0: SVM/RVI
> efifb at mainbus0 not configured
> dt: 445 probes
> uvideo0 at uhub1 port 2 configuration 1 interface 0 "Azurewave Integrated
> Camera" rev 2.01/17.11 addr 2
> video0 at uvideo0
> vscsi0 at root
> scsibus2 at vscsi0: 256 targets
> softraid0 at root
> scsibus3 at softraid0: 256 targets
> root on sd0a (3a85b6926424009b.a) swap on sd0b dump on sd0b
> iwm0: hw rev 0x230, fw ver 34.0.1, address a0:51:0b:ed:56:de
> amdgpu0: RAVEN 8 CU rev 0x01
> amdgpu0: 1920x1080, 32bpp
> wsdisplay0 at amdgpu0 mux 1: console (std, vt100 emulation), using wskbd0
> wsdisplay0: screen 1-5 added (std, vt100 emulation)
> drm:pid71504:amdgpu_bo_pin_restricted *ERROR* 0xffff800001836e18 pin failed
> [drm] *ERROR* Failed to pin framebuffer with error -12
This occurs when starting X (and not every time) on raven ridge
and picasso systems since the 5.10 drm changes went in.
With a t495 when this happens
ttm_bo_mem_space() ret -ENOMEM
ttm_bo_move_buffer()
ttm_bo_validate()
amdgpu_bo_pin_restricted()
No space for 0xffff8000018231e8 (2224 pages, 8896K, 8M)
placement[0]=0x006E0000 (2)
ttm_placement.h:#define TTM_PL_VRAM 2
[drm] vm size is 262144 GB, 4 levels, block size is 9-bit, fragment size is
9-bit
drm: VRAM: 2048M 0x000000F400000000 - 0x000000F47FFFFFFF (2048M used)
drm: GART: 1024M 0x0000000000000000 - 0x000000003FFFFFFF
drm: AGP: 267419648M 0x000000F800000000 - 0x0000FFFFFFFFFFFF
[drm] Detected VRAM RAM=2048M, BAR=2048M
[drm] RAM width 64bits DDR4
[TTM] Zone kernel: Available graphics memory: 7269782 KiB
[TTM] Zone dma32: Available graphics memory: 2097152 KiB
[TTM] Initializing pool allocator
[drm] amdgpu: 2048M of VRAM memory ready
[drm] amdgpu: 3072M of GTT memory ready.
[drm] GART: num cpu pages 262144, num gpu pages 262144
[drm] PCIE GART of 1024M enabled (table at 0x000000F400900000).
[drm] vram apper at 0x3BF000000
[drm] size 8294400
[drm] fb depth is 24
[drm] pitch is 7680
Can you try the following diff to revert to the 5.7 drm_mm ?
I have not been able to reproduce the problem on t495/picasso
with this change.
Index: sys/dev/pci/drm/include/drm/drm_mm.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/include/drm/drm_mm.h,v
retrieving revision 1.3
diff -u -p -r1.3 drm_mm.h
--- sys/dev/pci/drm/include/drm/drm_mm.h 7 Jul 2021 02:38:36 -0000
1.3
+++ sys/dev/pci/drm/include/drm/drm_mm.h 8 Jul 2021 06:25:32 -0000
@@ -168,7 +168,6 @@ struct drm_mm_node {
struct rb_node rb_hole_addr;
u64 __subtree_last;
u64 hole_size;
- u64 subtree_max_hole;
unsigned long flags;
#define DRM_MM_NODE_ALLOCATED_BIT 0
#define DRM_MM_NODE_SCANNED_BIT 1
@@ -338,7 +337,7 @@ static inline u64 drm_mm_hole_node_end(c
/**
* drm_mm_nodes - list of nodes under the drm_mm range manager
- * @mm: the struct drm_mm range manager
+ * @mm: the struct drm_mm range manger
*
* As the drm_mm range manager hides its node_list deep with its
* structure, extracting it looks painful and repetitive. This is
Index: sys/dev/pci/drm/drm_mm.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/drm_mm.c,v
retrieving revision 1.12
diff -u -p -r1.12 drm_mm.c
--- sys/dev/pci/drm/drm_mm.c 7 Jul 2021 02:38:21 -0000 1.12
+++ sys/dev/pci/drm/drm_mm.c 8 Jul 2021 06:24:31 -0000
@@ -240,6 +240,20 @@ static void drm_mm_interval_tree_add_nod
#endif
}
+#define DRM_RB_INSERT(root, member, expr) do { \
+ struct rb_node **link = &root.rb_node, *rb = NULL; \
+ u64 x = expr(node); \
+ while (*link) { \
+ rb = *link; \
+ if (x < expr(rb_entry(rb, struct drm_mm_node, member))) \
+ link = &rb->rb_left; \
+ else \
+ link = &rb->rb_right; \
+ } \
+ rb_link_node(&node->member, rb, link); \
+ rb_insert_color(&node->member, &root); \
+} while (0)
+
#define HOLE_SIZE(NODE) ((NODE)->hole_size)
#define HOLE_ADDR(NODE) (__drm_mm_hole_node_start(NODE))
@@ -269,48 +283,16 @@ static void insert_hole_size(struct rb_r
rb_insert_color_cached(&node->rb_hole_size, root, first);
}
-#ifdef notyet
-RB_DECLARE_CALLBACKS_MAX(static, augment_callbacks,
- struct drm_mm_node, rb_hole_addr,
- u64, subtree_max_hole, HOLE_SIZE)
-#endif
-
-static void insert_hole_addr(struct rb_root *root, struct drm_mm_node *node)
-{
- struct rb_node **link = &root->rb_node, *rb_parent = NULL;
- u64 start = HOLE_ADDR(node), subtree_max_hole = node->subtree_max_hole;
- struct drm_mm_node *parent;
-
- while (*link) {
- rb_parent = *link;
- parent = rb_entry(rb_parent, struct drm_mm_node, rb_hole_addr);
- if (parent->subtree_max_hole < subtree_max_hole)
- parent->subtree_max_hole = subtree_max_hole;
- if (start < HOLE_ADDR(parent))
- link = &parent->rb_hole_addr.rb_left;
- else
- link = &parent->rb_hole_addr.rb_right;
- }
-
- rb_link_node(&node->rb_hole_addr, rb_parent, link);
-#ifdef notyet
- rb_insert_augmented(&node->rb_hole_addr, root, &augment_callbacks);
-#else
- rb_insert_color(&node->rb_hole_addr, root);
-#endif
-}
-
static void add_hole(struct drm_mm_node *node)
{
struct drm_mm *mm = node->mm;
node->hole_size =
__drm_mm_hole_node_end(node) - __drm_mm_hole_node_start(node);
- node->subtree_max_hole = node->hole_size;
DRM_MM_BUG_ON(!drm_mm_hole_follows(node));
insert_hole_size(&mm->holes_size, node);
- insert_hole_addr(&mm->holes_addr, node);
+ DRM_RB_INSERT(mm->holes_addr, rb_hole_addr, HOLE_ADDR);
list_add(&node->hole_stack, &mm->hole_stack);
}
@@ -321,14 +303,8 @@ static void rm_hole(struct drm_mm_node *
list_del(&node->hole_stack);
rb_erase_cached(&node->rb_hole_size, &node->mm->holes_size);
-#ifdef notyet
- rb_erase_augmented(&node->rb_hole_addr, &node->mm->holes_addr,
- &augment_callbacks);
-#else
rb_erase(&node->rb_hole_addr, &node->mm->holes_addr);
-#endif
node->hole_size = 0;
- node->subtree_max_hole = 0;
DRM_MM_BUG_ON(drm_mm_hole_follows(node));
}
@@ -343,6 +319,11 @@ static inline struct drm_mm_node *rb_hol
return rb_entry_safe(rb, struct drm_mm_node, rb_hole_addr);
}
+static inline u64 rb_hole_size(struct rb_node *rb)
+{
+ return rb_entry(rb, struct drm_mm_node, rb_hole_size)->hole_size;
+}
+
static struct drm_mm_node *best_hole(struct drm_mm *mm, u64 size)
{
struct rb_node *rb = mm->holes_size.rb_root.rb_node;
@@ -363,12 +344,7 @@ static struct drm_mm_node *best_hole(str
return best;
}
-static bool usable_hole_addr(struct rb_node *rb, u64 size)
-{
- return rb && rb_hole_addr_to_node(rb)->subtree_max_hole >= size;
-}
-
-static struct drm_mm_node *find_hole_addr(struct drm_mm *mm, u64 addr, u64
size)
+static struct drm_mm_node *find_hole(struct drm_mm *mm, u64 addr)
{
struct rb_node *rb = mm->holes_addr.rb_node;
struct drm_mm_node *node = NULL;
@@ -376,9 +352,6 @@ static struct drm_mm_node *find_hole_add
while (rb) {
u64 hole_start;
- if (!usable_hole_addr(rb, size))
- break;
-
node = rb_hole_addr_to_node(rb);
hole_start = __drm_mm_hole_node_start(node);
@@ -404,10 +377,10 @@ first_hole(struct drm_mm *mm,
return best_hole(mm, size);
case DRM_MM_INSERT_LOW:
- return find_hole_addr(mm, start, size);
+ return find_hole(mm, start);
case DRM_MM_INSERT_HIGH:
- return find_hole_addr(mm, end, size);
+ return find_hole(mm, end);
case DRM_MM_INSERT_EVICT:
return list_first_entry_or_null(&mm->hole_stack,
@@ -416,45 +389,9 @@ first_hole(struct drm_mm *mm,
}
}
-/**
- * DECLARE_NEXT_HOLE_ADDR - macro to declare next hole functions
- * @name: name of function to declare
- * @first: first rb member to traverse (either rb_left or rb_right).
- * @last: last rb member to traverse (either rb_right or rb_left).
- *
- * This macro declares a function to return the next hole of the addr rb tree.
- * While traversing the tree we take the searched size into account and only
- * visit branches with potential big enough holes.
- */
-
-#define DECLARE_NEXT_HOLE_ADDR(name, first, last) \
-static struct drm_mm_node *name(struct drm_mm_node *entry, u64 size) \
-{ \
- struct rb_node *parent, *node = &entry->rb_hole_addr; \
- \
- if (!entry || RB_EMPTY_NODE(node)) \
- return NULL; \
- \
- if (usable_hole_addr(node->first, size)) { \
- node = node->first; \
- while (usable_hole_addr(node->last, size)) \
- node = node->last; \
- return rb_hole_addr_to_node(node); \
- } \
- \
- while ((parent = rb_parent(node)) && node == parent->first) \
- node = parent; \
- \
- return rb_hole_addr_to_node(parent); \
-}
-
-DECLARE_NEXT_HOLE_ADDR(next_hole_high_addr, rb_left, rb_right)
-DECLARE_NEXT_HOLE_ADDR(next_hole_low_addr, rb_right, rb_left)
-
static struct drm_mm_node *
next_hole(struct drm_mm *mm,
struct drm_mm_node *node,
- u64 size,
enum drm_mm_insert_mode mode)
{
switch (mode) {
@@ -463,10 +400,10 @@ next_hole(struct drm_mm *mm,
return rb_hole_size_to_node(rb_prev(&node->rb_hole_size));
case DRM_MM_INSERT_LOW:
- return next_hole_low_addr(node, size);
+ return rb_hole_addr_to_node(rb_next(&node->rb_hole_addr));
case DRM_MM_INSERT_HIGH:
- return next_hole_high_addr(node, size);
+ return rb_hole_addr_to_node(rb_prev(&node->rb_hole_addr));
case DRM_MM_INSERT_EVICT:
node = list_next_entry(node, hole_stack);
@@ -500,7 +437,7 @@ int drm_mm_reserve_node(struct drm_mm *m
return -ENOSPC;
/* Find the relevant hole to add our node to */
- hole = find_hole_addr(mm, node->start, 0);
+ hole = find_hole(mm, node->start);
if (!hole)
return -ENOSPC;
@@ -580,7 +517,7 @@ int drm_mm_insert_node_in_range(struct d
remainder_mask = is_power_of_2(alignment) ? alignment - 1 : 0;
for (hole = first_hole(mm, range_start, range_end, size, mode);
hole;
- hole = once ? NULL : next_hole(mm, hole, size, mode)) {
+ hole = once ? NULL : next_hole(mm, hole, mode)) {
u64 hole_start = __drm_mm_hole_node_start(hole);
u64 hole_end = hole_start + hole->hole_size;
u64 adj_start, adj_end;
