Hi, I would like to follow up on submitted patch, is there any concern on applying it for vte(4) driver (as well as adding new PHY models to rdcphy(4): https://marc.info/?l=openbsd-bugs&m=163105121012387&w=2 to rdcphy)? It would be helpful for me to avoid patching it manually. Thank you.
Regards, Andrius V On Mon, Sep 13, 2021 at 1:42 PM Andrius V <[email protected]> wrote: > > Hi, > > On some Vortex86 SoCs MDC speed control register needs to be restored > to original value after MAC reset. This issue happens if MAC has non > default VTE_MDCSC register value before reset, and it is erroneously > set to default after, thus causing certain PHY registers fail to be > read. Since PHY registers determine link status, the link is never > established (ifconfig media shows "none" value). Also, one obvious > sign is incorrect oui value in dmesg (0x3ffff4 instead of the one > defined in MII_OUI_RDC). > > Initially, I found and fixed that in NetBSD, but it affects all BSDs > and Linux. Patch is already applied on NetBSD > (http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/dev/pci/if_vte.c.diff?r1=1.31&r2=1.32) > and Linux netdev branch > (https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/commit/?id=e3f0cc1a945fcefec0c7c9d9dfd028a51daa1846). > Sending the same patch for OpenBSD. For more info and my debugging > history can be found in > http://gnats.netbsd.org/cgi-bin/query-pr-single.pl?number=53494 > thread. I tested the patch on my Vortex86DX3 (link is established/oui > is correct), DX2 based machines on OpenBSD (but the patch itself was > tested by few more people in NetBSD/Linux too). > > This patch is loosely related to my request to add new PHY models, but > can be applied independently, since vte(4) works with generic PHY > driver as well. > > --- > Index: sys/dev/pci/if_vte.c > =================================================================== > RCS file: /cvs/src/sys/dev/pci/if_vte.c,v > retrieving revision 1.24 > diff -u -p -u -p -r1.24 if_vte.c > --- sys/dev/pci/if_vte.c 10 Jul 2020 13:26:38 -0000 1.24 > +++ sys/dev/pci/if_vte.c 13 Sep 2021 10:22:06 -0000 > @@ -1084,9 +1084,10 @@ vte_tick(void *arg) > void > vte_reset(struct vte_softc *sc) > { > - uint16_t mcr; > + uint16_t mcr, mdcsc; > int i; > > + mdcsc = CSR_READ_2(sc, VTE_MDCSC); > mcr = CSR_READ_2(sc, VTE_MCR1); > CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); > for (i = VTE_RESET_TIMEOUT; i > 0; i--) { > @@ -1105,6 +1106,14 @@ vte_reset(struct vte_softc *sc) > CSR_WRITE_2(sc, VTE_MACSM, 0x0002); > CSR_WRITE_2(sc, VTE_MACSM, 0); > DELAY(5000); > + > + /* > + * On some SoCs (like Vortex86DX3) MDC speed control register value > + * needs to be restored to original value instead of default one, > + * otherwise some PHY registers may fail to be read. > + */ > + if (mdcsc != MDCSC_DEFAULT) > + CSR_WRITE_2(sc, VTE_MDCSC, mdcsc); > } > > int > ---- > > Regards, > Andrius V
