On Thu, 21 Apr 2022 at 00:47:05 +1000, Jonathan Gray wrote:
> On Wed, Apr 20, 2022 at 09:14:19AM -0500, joshua stein wrote:
> > I noticed in a few dmesgs from Intel 11th gen machines, the L2 cache
> > is printed as disabled. Is there some new MSR that needs to be read
> > on these CPUs?
>
> l2 cache information is taken from cpuid 0x80000006
>
> Intel documents cpuid eax 0x80000006 in the SDM as
>
> EAX Reserved = 0.
> EBX Reserved = 0.
>
> ECX Bits 07 - 00: Cache Line size in bytes.
> Bits 11 - 08: Reserved.
> Bits 15 - 12: L2 Associativity field *.
> Bits 31 - 16: Cache size in 1K units.
>
> EDX Reserved = 0.
>
> * L2 associativity field encodings: 08H - 16 ways
> 09H - Reserved
> 00H - Disabled 0AH - 32 ways
> 01H - 1 way (direct mapped) 0BH - 48 ways
> 02H - 2 ways 0CH - 64 ways
> 03H - Reserved 0DH - 96 ways
> 04H - 4 ways 0EH - 128 ways
> 05H - Reserved 0FH - Fully associative
> 06H - 8 ways
> 07H - See CPUID leaf 04H, sub-leaf 2**
>
> ** CPUID leaf 04H provides details of deterministic cache parameters,
> including the L2 cache in sub-leaf 2
>
> Do you see 7 for the l2 associativity value?
Yes, the full ECX value is 0x1007040
> (0x1007040 >> 12) & 0xff
=> 7
