On Fri, Sep 29, 2023 at 10:09:17PM +0200, Solène Rapenne wrote:
> amdgpu_bar_sizes: RBCAP0 0x3f000 sizes: 256M 512M 1G 2G 4G 8G
> amdgpu_bar_sizes: RBCTRL0 0xd40 8G
> GMC real 0x1ff000000 vis 0x1ff000000, FB off 0x7c00000000 size 0x200000000,
> gart size 0x20000000
Does limiting to a 32-bit size help?
Index: sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c,v
retrieving revision 1.14
diff -u -p -r1.14 amdgpu_ttm.c
--- sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c 13 Aug 2023 10:36:26 -0000
1.14
+++ sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c 2 Oct 2023 10:48:45 -0000
@@ -1791,6 +1791,13 @@ int amdgpu_ttm_init(struct amdgpu_device
return r;
}
+#ifdef __OpenBSD__
+ if (amdgpu_vis_vram_limit == 0 && ((adev->flags & AMD_IS_APU) == 0)) {
+ if (amdgpu_vis_vram_limit > 4096)
+ amdgpu_vis_vram_limit = 4096;
+ }
+#endif
+
/* Reduce size of CPU-visible VRAM if requested */
vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
if (amdgpu_vis_vram_limit > 0 &&
@@ -1810,11 +1817,13 @@ int amdgpu_ttm_init(struct amdgpu_device
adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
adev->gmc.visible_vram_size);
#else
- if (bus_space_map(adev->memt, adev->gmc.aper_base,
+ r = bus_space_map(adev->memt, adev->gmc.aper_base,
adev->gmc.visible_vram_size,
BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE,
- &adev->mman.aper_bsh)) {
+ &adev->mman.aper_bsh);
+ if (r) {
adev->mman.aper_base_kaddr = NULL;
+ printf("bus_space_map ret %d\n", r);
} else {
adev->mman.aper_base_kaddr = bus_space_vaddr(adev->memt,
adev->mman.aper_bsh);