On Sun, Feb 18, 2024 at 09:01:13PM +0100, Kirill A. Korinsky wrote:
> Greetings,
>
> Here an ugly patch which recovers support of LG UltraFine 5K which was broken
> since update drm to linux 6.6.12.
>
> This Display is quite delicate if not to say unstable, and it won't start with
> timeout other whan 250ms.
>
> A function intel_pxp_get_backend_timeout_ms returns two possible value: 250 or
> GSCFW_MAX_ROUND_TRIP_LATENCY_MS which is defined at the end as 40 * 50.
>
> Before an update, this code has only 250 as timeout and it works.
>
> Possible that intel_pxp_init doesn't initialize pxp->ctrl_gt the same way like
> linux, or such regression exists on linux as well.
I'm curious if some of the newer commits in linux change what you see.
combined diff below
commit 698e19da2914a0021a088b2b5d101d1854862315
Author: Zhanjun Dong <zhanjun.d...@intel.com>
Date: Mon Nov 13 14:49:53 2023 -0800
drm/i915: Skip pxp init if gt is wedged
commit fb99e79ee62aaa07d9e77cb3a15c5f1ae2790e6a
Author: Alan Previn <alan.previn.teres.ale...@intel.com>
Date: Wed Oct 11 14:01:57 2023 +0300
mei: update mei-pxp's component interface with timeouts
commit 8ae272348153ed2fa423f739047a592d9bd55ba2
Author: Alan Previn <alan.previn.teres.ale...@intel.com>
Date: Sun Sep 17 14:19:31 2023 -0700
drm/i915/pxp/mtl: Update pxp-firmware response timeout
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=698e19da2914a0021a088b2b5d101d1854862315
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fb99e79ee62aaa07d9e77cb3a15c5f1ae2790e6a
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8ae272348153ed2fa423f739047a592d9bd55ba2
diff --git sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
index 89ed5ee9cde..2fde5c360cf 100644
--- sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
+++ sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
@@ -81,8 +81,17 @@ out_rq:
i915_request_add(rq);
- if (!err && i915_request_wait(rq, 0, msecs_to_jiffies(500)) < 0)
- err = -ETIME;
+ if (!err) {
+ /*
+ * Start timeout for i915_request_wait only after considering
one possible
+ * pending GSC-HECI submission cycle on the other
(non-privileged) path.
+ */
+ if (wait_for(i915_request_started(rq),
GSC_HECI_REPLY_LATENCY_MS))
+ drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm,
+ "Delay in gsc-heci-priv submission to
gsccs-hw");
+ if (i915_request_wait(rq, 0,
msecs_to_jiffies(GSC_HECI_REPLY_LATENCY_MS)) < 0)
+ err = -ETIME;
+ }
i915_request_put(rq);
@@ -186,6 +195,13 @@ out_rq:
i915_request_add(rq);
if (!err) {
+ /*
+ * Start timeout for i915_request_wait only after considering
one possible
+ * pending GSC-HECI submission cycle on the other (privileged)
path.
+ */
+ if (wait_for(i915_request_started(rq),
GSC_HECI_REPLY_LATENCY_MS))
+ drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm,
+ "Delay in gsc-heci-non-priv submission to
gsccs-hw");
if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
msecs_to_jiffies(timeout_ms)) < 0)
err = -ETIME;
diff --git sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
index 09d3fbdad05..c4308291c00 100644
--- sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
+++ sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
@@ -12,6 +12,12 @@ struct i915_vma;
struct intel_context;
struct intel_gsc_uc;
+#define GSC_HECI_REPLY_LATENCY_MS 500
+/*
+ * Max FW response time is 500ms, but this should be counted from the time the
+ * command has hit the GSC-CS hardware, not the preceding handoff to GuC CTB.
+ */
+
struct intel_gsc_mtl_header {
u32 validity_marker;
#define GSC_HECI_VALIDITY_MARKER 0xA578875A
diff --git sys/dev/pci/drm/i915/i915_driver.c sys/dev/pci/drm/i915/i915_driver.c
index 059fdca5d58..b5870fe9b26 100644
--- sys/dev/pci/drm/i915/i915_driver.c
+++ sys/dev/pci/drm/i915/i915_driver.c
@@ -810,7 +810,9 @@ int i915_driver_probe(struct drm_i915_private *i915, const
struct pci_device_id
if (ret)
goto out_cleanup_modeset2;
- intel_pxp_init(i915);
+ ret = intel_pxp_init(i915);
+ if (ret != -ENODEV)
+ drm_dbg(&i915->drm, "pxp init failed with %d\n", ret);
ret = intel_display_driver_probe(i915);
if (ret)
diff --git sys/dev/pci/drm/i915/pxp/intel_pxp.c
sys/dev/pci/drm/i915/pxp/intel_pxp.c
index e079f5b6ee6..41ac603e1a7 100644
--- sys/dev/pci/drm/i915/pxp/intel_pxp.c
+++ sys/dev/pci/drm/i915/pxp/intel_pxp.c
@@ -199,6 +199,9 @@ int intel_pxp_init(struct drm_i915_private *i915)
struct intel_gt *gt;
bool is_full_feature = false;
+ if (intel_gt_is_wedged(to_gt(i915)))
+ return -ENOTCONN;
+
/*
* NOTE: Get the ctrl_gt before checking intel_pxp_is_supported since
* we still need it if PXP's backend tee transport is needed.
diff --git sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c
sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c
index 86f58a5bddd..cc81a462492 100644
--- sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c
+++ sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c
@@ -111,7 +111,7 @@ gsccs_send_message(struct intel_pxp *pxp,
ret = intel_gsc_uc_heci_cmd_submit_nonpriv(>->uc.gsc,
exec_res->ce, &pkt,
exec_res->bb_vaddr,
- GSC_REPLY_LATENCY_MS);
+ GSC_HECI_REPLY_LATENCY_MS);
if (ret) {
drm_err(&i915->drm, "failed to send gsc PXP msg (%d)\n", ret);
goto unlock;
diff --git sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h
sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h
index 298ad38e6c7..9aae779c4da 100644
--- sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h
+++ sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h
@@ -8,16 +8,14 @@
#include <linux/types.h>
+#include "gt/uc/intel_gsc_uc_heci_cmd_submit.h"
+
struct intel_pxp;
-#define GSC_REPLY_LATENCY_MS 210
-/*
- * Max FW response time is 200ms, to which we add 10ms to account for overhead
- * such as request preparation, GuC submission to hw and pipeline completion
times.
- */
#define GSC_PENDING_RETRY_MAXCOUNT 40
#define GSC_PENDING_RETRY_PAUSE_MS 50
-#define GSCFW_MAX_ROUND_TRIP_LATENCY_MS (GSC_PENDING_RETRY_MAXCOUNT *
GSC_PENDING_RETRY_PAUSE_MS)
+#define GSCFW_MAX_ROUND_TRIP_LATENCY_MS (GSC_HECI_REPLY_LATENCY_MS + \
+ (GSC_PENDING_RETRY_MAXCOUNT *
GSC_PENDING_RETRY_PAUSE_MS))
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_gsccs_fini(struct intel_pxp *pxp);
diff --git sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c
sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c
index eac254fc017..1970aef3120 100644
--- sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c
+++ sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c
@@ -20,6 +20,8 @@
#include "intel_pxp_tee.h"
#include "intel_pxp_types.h"
+#define PXP_TRANSPORT_TIMEOUT_MS 5000 /* 5 sec */
+
static bool
is_fw_err_platform_config(u32 type)
{
@@ -71,13 +73,15 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
goto unlock;
}
- ret = pxp_component->ops->send(pxp_component->tee_dev, msg_in,
msg_in_size);
+ ret = pxp_component->ops->send(pxp_component->tee_dev, msg_in,
msg_in_size,
+ PXP_TRANSPORT_TIMEOUT_MS);
if (ret) {
drm_err(&i915->drm, "Failed to send PXP TEE message\n");
goto unlock;
}
- ret = pxp_component->ops->recv(pxp_component->tee_dev, msg_out,
msg_out_max_size);
+ ret = pxp_component->ops->recv(pxp_component->tee_dev, msg_out,
msg_out_max_size,
+ PXP_TRANSPORT_TIMEOUT_MS);
if (ret < 0) {
drm_err(&i915->drm, "Failed to receive PXP TEE message\n");
goto unlock;
diff --git sys/dev/pci/drm/include/drm/i915_pxp_tee_interface.h
sys/dev/pci/drm/include/drm/i915_pxp_tee_interface.h
index a702b6ec17f..7d96985f2d0 100644
--- sys/dev/pci/drm/include/drm/i915_pxp_tee_interface.h
+++ sys/dev/pci/drm/include/drm/i915_pxp_tee_interface.h
@@ -22,8 +22,10 @@ struct i915_pxp_component_ops {
*/
struct module *owner;
- int (*send)(struct device *dev, const void *message, size_t size);
- int (*recv)(struct device *dev, void *buffer, size_t size);
+ int (*send)(struct device *dev, const void *message, size_t size,
+ unsigned long timeout_ms);
+ int (*recv)(struct device *dev, void *buffer, size_t size,
+ unsigned long timeout_ms);
ssize_t (*gsc_command)(struct device *dev, u8 client_id, u32 fence_id,
struct scatterlist *sg_in, size_t total_in_len,
struct scatterlist *sg_out);
