#3007: ARM caching issues
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Reporter: munster | Owner: joel.sherrill@…
Type: defect | Status: new
Priority: normal | Milestone: 4.12
Component: bsps | Version: 4.12
Severity: normal | Keywords: ARM,cache,L2C 310
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There are two problems with the caching on ARM:
* In cases where the buffer is not aligned to line boundary at the
beginning or the end, the invalidate operation would lose modifications
done on the adjacent data. This applies to both L1 and L2 caches.
* The L2C-310 cache management operations use excessive locking. According
to
[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246f/Beicdhde.html
manual], the used operations (Clean Line by PA, Clean and Invalidate Line
by PA, Cache Sync) are atomic and do not require locking.
I have attached the proposed patch.
--
Ticket URL: <http://devel.rtems.org/ticket/3007>
RTEMS Project <http://www.rtems.org/>
RTEMS Project
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