#3433: Add SMP support for RISC-V
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Reporter: Sebastian Huber | Owner: Sebastian Huber
Type: project | Status: accepted
Priority: normal | Milestone: 6.1
Component: arch/riscv | Version:
Severity: normal | Resolution:
Keywords: | Blocked By: 3452, 3453, 3459
Blocking: |
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Comment (by Sebastian Huber <sebastian.huber@…>):
In [changeset:"9510742e7ff48c3df177ec9f7b5e0d229c696e85/rtems"
9510742/rtems]:
{{{
#!CommitTicketReference repository="rtems"
revision="9510742e7ff48c3df177ec9f7b5e0d229c696e85"
riscv: Fix CPU_STACK_ALIGNMENT
According to the RISC-V psABI
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
the stack alignment is 128 bits (16 bytes).
Update #3433.
}}}
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Ticket URL: <http://devel.rtems.org/ticket/3433#comment:29>
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