#4202: Add BSP for ARM Fixed Virtual Platform with a Cortex-R52
-----------------------------+------------------------------
Reporter: Sebastian Huber | Owner: Sebastian Huber
Type: enhancement | Status: assigned
Priority: normal | Milestone: 6.1
Component: arch/arm | Version: 6
Severity: normal | Resolution:
Keywords: | Blocked By:
Blocking: |
-----------------------------+------------------------------
Comment (by Sebastian Huber <sebastian.huber@…>):
In [changeset:"e164df5e33608576443b4cd5923a9046358ee773/rtems"
e164df5e/rtems]:
{{{
#!CommitTicketReference repository="rtems"
revision="e164df5e33608576443b4cd5923a9046358ee773"
bsps/arm: Clear SCTLR[M, I, A, C] in start.S
Initialize the data and unified cache levels. Invalidate the
instruction cache levels.
Update #4202.
}}}
--
Ticket URL: <http://devel.rtems.org/ticket/4202#comment:20>
RTEMS Project <http://www.rtems.org/>
RTEMS Project
_______________________________________________
bugs mailing list
[email protected]
http://lists.rtems.org/mailman/listinfo/bugs
