Sebastian Huber pushed new commits to merge request !255 Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/255
* 07217e3f - bsps/aarch64: Customize EL2/EL3 start support * 8d6e8f15 - aarch64: Split exception support * 2b364923 - aarch64: Move exception frame support * a8d3efe4 - dev/irq: Simplify GICv2 set/get affinity * 8db6a450 - bsps: Assembly implementation for PSCI bsp_reset() * f630be89 - aarch64/xilinx-zynqmp: Simplify startup * 1524b5f9 - aarch64/xilinx-zynqmp: Move get I2C clocks * 5ff5bd3c - aarch64: More robust SMP system start * 5a962e3b - arm/aarch64: Optimize _CPU_SMP_Send_interrupt() * 42c6f727 - dev/irq: Remove arm_gic_irq_generate_software_irq() * c538079e - aarch64: Remove trapped FP exceptions support * f43042cd - bsps: Move <bsp/linker-symbols.h> to shared * 3fd06315 - dev/irq: Simplify SMP GIC initialization * cfd88585 - bsps/aarch64: Use fatal error for data cache disable * 77094f11 - bsps/aarch64: Simplify I-cache invalidate * 098f8cb0 - bsps/aarch64: Fix AArch64_get_ccsidr_for_level() * 064a672f - bsps/aarch64: Simplify AArch64_clidr_get_cache_type() * aac76058 - bsps/aarch64: Fix entire data cache flush/invalidate * 41ed4b5d - bsps/aarch64: Assume that all levels have a data cache * 8c4cc767 - aarch64/xilinx-zynqmp: Move MMU config table -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/255 You're receiving this email because of your account on gitlab.rtems.org.
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