Ranulfo Raphael commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/804#note_135079 The main differences are related to the QSPI `connection mode`, `bank selection` and the `Status Register` handling. This driver is based on the Xilinx example for QSPI flash `bigger then 128Mbits`. The other examples the Xilinx provides acts like the `zynq-flash`. In stacked mode connection, it setups the proper `lower` and `upper` page depending on the flash memory being accessed. It also supports parallel mode. For bank selection, the driver switches banks at each `16MB` according to the flash address. Regarding the Status Register, the `zynq-flash` defines Status Register bits as: `[SRWD P_ERR E_ERR BP2 BP1 BP0 WEL WIP]` However, some flash devices defines: `[SRWD BP3 TB BP2 BP1 BP0 WEL WIP]` The bank selection, protection bits and registers, I have followed the `N25Q00AA` datasheet. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/804#note_135079 You're receiving this email because of your account on gitlab.rtems.org.
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