Sam Price commented on a discussion on cpukit/score/cpu/microblaze/cpu.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/841#note_136932 > + > + /* See ug984-vivado-microblaze-ref Exception Status Register (ESR) */ > + _CPU_esr_ec_code esr_ec_codes[] = { > + {0, "Stream Exception"}, > + {1, "Unaligned data access exception"}, > + {2,"Illegal op-code exception"}, > + {3, "Instruction bus error exception"}, > + {4, "Data bus error exception"}, > + {5, "Divide exception"}, > + {6,"Floating point unit exception"}, > + {7, "Privileged instruction or Stack protection violation exception"}, /* > Xilinx docs have 2 errors for this id */ > + {16,"Data storage exception"}, > + {17,"Instruction storage exception"}, > + {18,"Data TLB miss exception"}, > + {19,"Instruction TLB miss exception"} > + }; Pulled up, tried apply a clang tidy file, struggling with pipeline. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/841#note_136932 You're receiving this email because of your account on gitlab.rtems.org.
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