Rémi Debord commented on a discussion on spec/build/bsps/arm/xilinx-versal-rpu/optmemdevplori.yml: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/904#note_138657 > +- env-assign: null > +- format-and-define: null > +build-type: option > +copyrights: > +- Copyright (C) 2026 Airbus Defence and Space > +default: > +- enabled-by: true > + value: 0x80000000 > +description: | > + This option defines the address of the PL device memory area > + (PS to PL AXI Interface from LPD). > +enabled-by: true > +format: '{:#010x}' > +links: [] > +name: VERSAL_MEMORY_DEVPL_ORIGIN > +type: build Right, range is removed in the third commit. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/904#note_138657 You're receiving this email because of your account on gitlab.rtems.org.
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