Sam Price started a new discussion on bsps/microblaze/microblaze_fpga/irq/irq.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/980#note_140686 > } > > rtems_status_code bsp_interrupt_raise( rtems_vector_number vector ) > { > - (void) vector; > + if ( vector == microblaze_tm27_alt_vector() ) { > + uint32_t mer; > + > + /* > + * Generate a software interrupt by writing ISR while HIE is clear > + * (Xilinx AXI INTC PG099). > + */ > + mer = mblaze_intc->mer; > + mblaze_intc->mer = mer & ~MICROBLAZE_INTC_MER_HIE; > + mblaze_intc->isr = 1U << vector; > + mblaze_intc->mer = mer; Need to verify and add a comment from the xilinx guide. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/980#note_140686 You're receiving this email because of your account on gitlab.rtems.org.
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