xiaojun zheng commented on a discussion on bsps/aarch64/raspberrypi5/start/bspsmp.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1072#note_143382 > +{ > + uint32_t PSCI_FN_SYSTEM_CPU_ON = 0xC4000003; > + /* Core IDs are in AFF1 in the Pi5 */ > + uint64_t target_cpu = (uint64_t) cpu_index << 8; > + uint64_t ret; > + > + __asm__ volatile ( > + "mov x0, %1\n" > + "mov x1, %2\n" > + "mov x2, %3\n" > + "mov x3, #0\n" > + "smc #0\n" > + "mov %0, x0\n" > + : "=r" ( ret ) : "r" ( PSCI_FN_SYSTEM_CPU_ON ), "r" ( target_cpu ), > + "r" ( (uint64_t) _start ) : "x0", "x1", "x2", "x3", "memory" > + ); GICv3 also requires the MPIDR value when triggering SGIs. Is there a standardized way to establish an index-to-MPIDR mapping during core initialization, and to retrieve the MPIDR via a function like _AArch64_Get_MPIDR_for_cpu_index()? This would allow the AArch64 architecture to share the relevant code across different BSPs. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1072#note_143382 You're receiving this email because of your account on gitlab.rtems.org.
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