Amar Takhar commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5527#note_146305 S3 is a different architecture and tooling. C3, C5, C6, P4 are riscv which is all we support for ESP-32. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5527#note_146305 You're receiving this email because of your account on gitlab.rtems.org.
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