Gedare Bloom started a new discussion on bsps/riscv/esp32/irq/irq_c3.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147633 > + uint32_t cookie = riscv_interrupt_disable(); > + > + /* Enable all cpu-side interrupts */ > + MATRIX_REG( INTERRUPT_CORE0_CPU_INT_ENABLE_REG ) = 0xffffffffU; > + /* Set everything to level interrupts */ > + MATRIX_REG( INTERRUPT_CORE0_CPU_INT_TYPE_REG ) = 0x0U; > + for (uint8_t vec = 1; vec < RISCV_MAXIMUM_EXTERNAL_INTERRUPTS; vec++) { > + /* > + * RISCV_MAXIMUM_EXTERNAL_INTERRUPTS is a valid interrupt because 0 is > + * reserved for exceptions and not counted in the total number of > + * interrupts > + */ > + bsp_interrupt_set_priority(vec, 14); > + } > + > + __asm__ volatile ("fence o, i" : : : "memory"); We should probably have helpers for this kind of thing. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147633 You're receiving this email because of your account on gitlab.rtems.org.
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