Gedare Bloom commented on a discussion on cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1239#note_149902 > #define SATP_MODE_SHIFT (31) > #endif > > +#ifndef ASM > + > +#define _RISCV_FENCE( pred, succ ) \ > + __asm__ volatile ( "fence " #pred ", " #succ : : : "memory" ) > + > +static inline void _RISCV_data_barrier( void ) > +{ > + _RISCV_FENCE( rw, rw ); This is a good point. The fences probably should have had it, to prevent the compiler from reordering loads and stores. I have no idea if gcc is smart enough to avoid doing that. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1239#note_149902 You're receiving this email because of your account on gitlab.rtems.org.
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