Avi Weiss created an issue:
https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5613
## Summary
The `TMS570_HTU_INTOFF0` and `TMS570_HTU_INTOFF1` mask macros go slightly
outside their intended bounds - including bit field 10 as well (8-10) when it
should be only 8-9.
## Steps to reproduce
```c
/*---------------------TMS570_HTU_INTOFF0---------------------*/
/* field: INTTYPE0 - Interrupt Type of Interrupt Line 0. */
#define TMS570_HTU_INTOFF0_INTTYPE0(val) BSP_FLD32(val,8, 10)
#define TMS570_HTU_INTOFF0_INTTYPE0_GET(reg) BSP_FLD32GET(reg,8, 10)
#define TMS570_HTU_INTOFF0_INTTYPE0_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: CPOFF0 - CP Offset. */
#define TMS570_HTU_INTOFF0_CPOFF0(val) BSP_FLD32(val,0, 4)
#define TMS570_HTU_INTOFF0_CPOFF0_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_HTU_INTOFF0_CPOFF0_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
/*---------------------TMS570_HTU_INTOFF1---------------------*/
/* field: INTTYPE1 - INTTYPE1 Interrupt Type of Interrupt Line 1. */
#define TMS570_HTU_INTOFF1_INTTYPE1(val) BSP_FLD32(val,8, 10)
#define TMS570_HTU_INTOFF1_INTTYPE1_GET(reg) BSP_FLD32GET(reg,8, 10)
#define TMS570_HTU_INTOFF1_INTTYPE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: CPOFF1 - CP Offset. */
#define TMS570_HTU_INTOFF1_CPOFF1(val) BSP_FLD32(val,0, 4)
#define TMS570_HTU_INTOFF1_CPOFF1_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_HTU_INTOFF1_CPOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
```
See TRM for reference:
{width=734
height=246}
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View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5613
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