Issue created by Sebastian Huber: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5808
Assignee: Sebastian Huber ## Summary The SPARC CPU port has these defects: - The context switch saves and restores no FSR. A thread runs with the rounding mode and the accrued exceptions of its predecessor. The predecessor later resumes with the values of its successor. A new thread starts with the FSR of the last floating-point user. The GR740 shows this in the uniprocessor and in the SMP configuration. - In SMP configurations, the default exception handler computes the address of the interrupt stack with an `smul` instruction. The instruction overwrites the Y register before the handler saves it. The exception frame then holds the product and not the Y register of the trapped context. - The port provides no `_CPU_Exception_resume()`. A fatal error extension which receives an exception frame cannot continue the trapped context. - No validation test checks the context switch, the interrupt processing, the register windows, the default exception handler or the exception resume of the port. The tm27 support of erc32 is not usable by a validation test. It includes no header which declares its interrupt sources, and it defines no `TM27_INTERRUPT_VECTOR_DEFAULT`. ## Proposal Save and restore the FSR in the context switch, and give each new context an initial FSR with NS set. Save the Y register before the multiplication in the default exception handler. Add `_CPU_Exception_resume()`. Add validation tests which load a pattern into every register which the port has to preserve, and compare what arrives. Each test proves that each of its checks can fail. It runs its scenario once per register with the pattern of that register inverted, and requires that exactly the checks of that register fail. The floating-point unit of the ERC32 implements no NS bit, so the tests compare the NS bit only where the floating-point unit implements it. Make the tm27 support of erc32 self-contained and provide its interrupt vector. This description was created with Claude Code assistance. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5808 You're receiving this email because of your account on gitlab.rtems.org. Unsubscribe from this thread: https://gitlab.rtems.org/-/namespace/49/sent_notifications/6-9gbrl3kxnebbgp50aaly22du0-1d/unsubscribe | Manage all notifications: https://gitlab.rtems.org/-/profile/notifications | Help: https://gitlab.rtems.org/help
_______________________________________________ bugs mailing list [email protected] http://lists.rtems.org/mailman/listinfo/bugs
