Sebastian Huber commented on a discussion on bsps/riscv/shared/irq/irq.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1536#note_160946 > > interrupt_count = riscv_plic_get_interrupt_count(); > > +#ifdef RISCV_PLIC_PROBE_PRIORITY_BITS > + /* > + * A PLIC has at least one interrupt source. The register keeps only the > + * implemented bits. The priority of the source is set by > + * riscv_plic_cpu_0_init() below. > + */ > + plic->priority[1] = UINT32_MAX; > + riscv_plic_maximum_priority = plic->priority[1]; The priorities are set to 1 in `riscv_plic_cpu_0_init()`. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1536#note_160946 You're receiving this email because of your account on gitlab.rtems.org. Unsubscribe from this thread: https://gitlab.rtems.org/-/namespace/49/sent_notifications/6-d6ew0itr5u5e1qvzn12em82hi-1d/unsubscribe | Manage all notifications: https://gitlab.rtems.org/-/profile/notifications | Help: https://gitlab.rtems.org/help
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