Sam Price created a merge request: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1549
Project:Branches: TheSamPrice/rtems:esp32c3-systimer-frequency to rtems/rtos/rtems:main Author: Sam Price `SYSTIMER_FREQUENCY` in `bsps/riscv/esp32/clock/clockdrv_systimer.c` is `16 * 1024 * 1024`, which is 16,777,216. The ESP32-C3 SYSTIMER actually counts at 16,000,000 Hz: it runs from the 40 MHz XTAL through a fixed divide-by-2.5. ESP-IDF uses the same rate. [`components/esp_hw_support/port/esp32c3/systimer.c`](https://github.com/espressif/esp-idf/blob/v5.4/components/esp_hw_support/port/esp32c3/systimer.c) says "40MHz/2.5 = 16MHz" and converts with `ticks / 16` per microsecond. The comments in this driver already say 16 MHz, including the "16count/interval" comment in `systimer_clock_initialize()`. This value sets the clock tick interval, the timecounter frequency and `_CPU_Counter_frequency()`. With the wrong value, each tick runs 4.9% long: 10.486 ms instead of 10 ms at the default 10 ms tick. Time also advances 4.6% too slowly, which loses about 67 minutes per day. `riscv/esp32c3db` builds with the change, including the testsuite, with no warnings. Not tested on hardware. Assisted-by: Claude Opus 5.5 (1M context) <[email protected]> -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1549 You're receiving this email because of your account on gitlab.rtems.org. Unsubscribe from this thread: https://gitlab.rtems.org/-/namespace/49/sent_notifications/6-5q5ntwmdijq8h5ukp9uf6qf13-1d/unsubscribe | Manage all notifications: https://gitlab.rtems.org/-/profile/notifications | Help: https://gitlab.rtems.org/help
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