> On Jul 3, 2018, at 12:23 AM, Toke Høiland-Jørgensen <[email protected]> wrote: > > My hunch is that this has something to do with the way mlx5 uses multiple > receive queues (and thus multiple CPUs). Which is probably different from > veth...
It doesn’t reproduce between between 2x APU2c4 (4 hardware queues and igb driver w/ mq support), but that’s 1Gbit, plus this Mellanox thing appears to have all sorts of hardware whatnots if this is the right device: http://www.mellanox.com/related-docs/prod_silicon/PB_ConnectX-4_EN_IC.pdf I noticed it has support for some link-layer congestion notification I’d not heard of until now (802.1Qau, https://www.ietf.org/proceedings/67/slides/tsvarea-2.pdf). _______________________________________________ Cake mailing list [email protected] https://lists.bufferbloat.net/listinfo/cake
