Hi Dan: That will be good. I will do my best. Hope I could help on Casper development. By the way, how does someone build designs for roach successfully without running BORPH?
Thanks Wan -----Original Message----- From: Dan Werthimer [mailto:[email protected]] Sent: Friday, 21 November 2008 2:59 PM To: Cheng, Wan (ATNF, Marsfield) Cc: Terry Filiba; Andrew Martens; Henry Chen; [email protected] Subject: Re: [casper] Casper 10.1 library issue hi wan, the roach board is brand new, and the library and tools are still buggy. some people are building designs for roach successfully, but there's still a long ways to go before everything works smoothly. for instance, we don't have BORPH working for ROACH yet. we expect it to be working in a few weeks. hayden is working on this. he just got a roach board last week. thanks for offering to help port. if you want to help porting and testing the libraries and tools for roach, terry filiba and andrew martens, who are cc'ed on this, can probably tell you which parts you can help us out on. glenn jones is another person who's been working hard porting libraries to 10.1. best wishes, dan [email protected] wrote: > Hi Dan: > > I am trying to understand more on your library development instead of > building something different. This is why I hope someone could give me more > explanation on how your library is developed. I would like to follow your > idea to extend or upgrade your library. But the case is it seems that I still > could not use 10.1 library for ROACH. I have to do something to speed up > instead of waiting for your library ready. I guess I could only work on the > modules I will use in my design if I could understand your library > development process. But unfortunately, there is less documents talking about > the casper library development process. I hope I could get some help at this > point. > > Thanks > > Wan > > -----Original Message----- > From: Dan Werthimer [mailto:[email protected]] > Sent: Friday, 21 November 2008 2:25 PM > To: Cheng, Wan (ATNF, Marsfield) > Cc: [email protected]; [email protected] > Subject: Re: [casper] Casper 10.1 library issue > > > wan, > > i strongly advising the standard bee_xps tools > that everyone in the casper collaboration > uses. if you use a different set of tools then > people won't be able to assist you, and your design > won't be able to be used by other people. > > best wishes, > > dan > > [email protected] wrote: >> Hi Henry: >> >> Why we have to use bee_xps to generate the bitstream instead useing sysgen? >> >> Wan >> >> >> >> -----Original Message----- >> From: Henry Chen [mailto:[email protected]] >> Sent: Friday, 21 November 2008 10:23 AM >> To: Cheng, Wan (ATNF, Marsfield) >> Cc: [email protected]; [email protected] >> Subject: Re: [casper] Casper 10.1 library issue >> >> Hi Wanxiang, >> >> If you have your Simulink set up as described at >> >> http://casper.berkeley.edu/wiki/index.php/MSSGE_Toolflow >> >> then your Simulink installation will automatically be able to >> access the scripts to enable you to use the toolflow. >> >> >> When you run the toolflow (bee_xps), that is basically the >> sequential execution of the gen_xps_files script that Andrew >> mentioned. >> >> -Henry >> >> For your question about >> >> [email protected] wrote: >>> Hi: >>> >>> Thanks Andrew. Any anyone know how we could use these matlab script >>> files? Are they linked to simulink automatically or we have to use them >>> during the library development manually? >>> >>> Thanks >>> >>> Wan >>> >>> ------------------------------------------------------------------------ >>> *From:* Andrew Martens [mailto:[email protected]] >>> *Sent:* Thursday, 20 November 2008 6:22 PM >>> *To:* Cheng, Wan (ATNF, Marsfield) >>> *Cc:* [email protected] >>> *Subject:* Re: [casper] Casper 10.1 library issue >>> >>> Hi Wan >>> >>> The directories in the toolflow are basically as follows; >>> >>> casper_library - DSP related scripts and libraries. >>> >>> xps_lib - contains the base EDK projects for the various hardware >>> platforms. These are copied and modified by the Matlab scripts according >>> to your design. >>> >>> xps_library - contains the Matlab scripts used to compile your design, >>> copy the base EDK project from xps_lib, modify it according to your >>> design, insert your design into the EDK project and synthesise and >>> place-and-route the finished design. These scripts also set up and >>> compile the software for the board. You may want to look at >>> gen_xps_files.m where you can follow the route this process takes. >>> >>> I don't know the full answer to your second question but you can make >>> System Generator generate HDL instead of a core. System Generator >>> internally must associate each block with HDL and parameters which it >>> uses to generate the final design. The best would be to look in the >>> documentation or on the web. >>> >>> Hope this helps. The best way to get to know the toolchain is to dive in >>> and try to figure it out yourself, you will soon get a good idea of what >>> is happening. >>> >>> Cheers >>> Andrew >>> >>> 2008/11/20 <[email protected]> >>> >>> Hi Andrew: >>> >>> Thanks for your information. I agree that it is not a simple process. >>> Except the casper_library and casper_library, there is another >>> mystery fold in 10.1 library, XPS_lib. Could you tell me what's this >>> for? >>> >>> Another question is: how sysgen could find correct HDL files/cores >>> when we generate bitstream? I guess there must be some link between >>> the simulink library and HDL file. Could you please what's they are? >>> >>> Thanks >>> >>> Wan >>> >>> -----Original Message----- >>> From: Henry Chen [mailto:[email protected] >>> <mailto:[email protected]>] >>> Sent: Monday, 3 November 2008 5:19 PM >>> To: [email protected] <mailto:[email protected]> >>> Cc: Cheng, Wan (ATNF, Marsfield) >>> Subject: Re: [casper] Casper 10.1 library issue >>> >>> Hi Wanxiang, >>> >>> The different FFTs are documented at >>> >>> http://casper.berkeley.edu/doc/mlib_devel_7_1/doc/html/node24.html >>> http://casper.berkeley.edu/doc/mlib_devel_7_1/doc/html/node25.html >>> http://casper.berkeley.edu/doc/mlib_devel_7_1/doc/html/node26.html >>> http://casper.berkeley.edu/doc/mlib_devel_7_1/doc/html/node27.html >>> >>> But in summary the base FFT block handles complex inputs and gives >>> complex outputs, and is completely parameterized to configure itself >>> for biplex (2 independent channel inputs) or wideband (single channel, >>> demultiplexed inputs). The real FFT takes real inputs and gives complex >>> outputs, discarding the complex conjugates. >>> >>> For information about the sync input, please see the memo at >>> >>> http://casper.berkeley.edu/memos/sync_memo_v1.pdf >>> >>> Thanks, >>> Henry >>> >>> [email protected] wrote: >>> > HI Andrew: >>> > >>> > Thank you for your answer. Now I have better idea on how the >>> libraries >>> > are organized. What I am do is to setup the simulink simulation. >>> Do you >>> > know the difference among several FFT module provided in the >>> casper library? >>> > >>> > They are : >>> > >>> > fft_biplex_real_2x >>> > fft_biplex_real_4x >>> > fft >>> > fft_wideband_real >>> > >>> > And by the way, what are the function for the shift and sync pin? >>> > >>> > Thanks >>> > >>> > Wan >>> > >>> > >>> ------------------------------------------------------------------------ >>> > *From:* Andrew Martens [mailto:[email protected] >>> <mailto:[email protected]>] >>> > *Sent:* Thursday, 30 October 2008 6:11 PM >>> > *To:* Cheng, Wan (ATNF, Marsfield) >>> > *Cc:* [email protected] <mailto:[email protected]>; >>> [email protected] <mailto:[email protected]> >>> > *Subject:* Re: [casper] Casper 10.1 library issue >>> > >>> > Hi Wan >>> > >>> > Matlab scripts generate and modify an EDK project containing the HDL >>> > code for the ADC. gen_xps_files.m (in xps_library directory) does >>> most >>> > of the work (look from line 246 or so) of copying a base EDK >>> project (in >>> > xps_lib directory) and then modifying it based on what your Simulink >>> > design contains. There are different base EDK projects for each >>> hardware >>> > platform. The base EDK project contains the HDL relevant to the >>> ADC (in >>> > pcores/adc_interface_*) and the Matlab script modifes other files >>> > (system.mhs, system.mss, data/system.ucf etc) to ensure the ADC >>> related >>> > infrastructure is included in the final EDK project. This is not >>> a very >>> > simple process and I am not sure where you want to jump in. >>> > >>> > Regards >>> > Andrew >>> > >>> > 2008/10/30 <[email protected]> >>> > >>> > HI Laura: >>> > >>> > Thanks for your help. You are right. If I set more samples per >>> > period, it is more difficult for me to find the difference. I >>> setup >>> > the sine wave according your setting, the difference is obvious. >>> > >>> > I think you explanation for the ADC internal structure is >>> correct. >>> > The extra delay in O1 is for alignment. But I still have one more >>> > question: >>> > >>> > How the ADC module is linked to the HDL code in the library? Some >>> > low level function, such as convert the DDR data into single >>> sample >>> > edge data, rebuffer the ADC clock, is done by HDL code. But I can >>> > not see how these HDL files are included into the design flow. Do >>> > you have any idea? >>> > >>> > Thanks >>> > >>> > Wan >>> > >>> > >>> ------------------------------------------------------------------------ >>> > *From:* Laura Spitler [mailto:[email protected] >>> <mailto:[email protected]> >>> > <mailto:[email protected] >>> <mailto:[email protected]>>] >>> > *Sent:* Thursday, 30 October 2008 1:48 AM >>> > >>> > *To:* Cheng, Wan (ATNF, Marsfield) >>> > *Cc:* [email protected] >>> <mailto:[email protected]> <mailto:[email protected] >>> <mailto:[email protected]>> >>> > *Subject:* Re: [casper] Casper 10.1 library issue >>> > >>> > Hi Wan, >>> > >>> > That is strange. I made a model that looks identical to your >>> AC_test >>> > using 10.1, and the output looks correct. >>> > Here are the parameters I'm using for the 'Sine Wave' block: >>> > Sine type : Sample based >>> > Amplitude: 1 >>> > Bias: 0 >>> > Samples per period: 10 >>> > Number of offset samples: 0 >>> > Sample time: 1/8 >>> > >>> > The sample time of the ADC block should be 1. >>> > >>> > The ADC block uses 4 or 8 downsample blocks for interleave >>> off and >>> > on respectively to mimic the parallel output of the ADC, which is >>> > why you have to set sample time to either 1/4 or 1/8. The >>> line with >>> > the delay block set to 2 rather than 1 is connected to the >>> > downsample block with offset sample = 0. My guess is the latency >>> > through the downsample block for the o0 sample is zero, so to >>> keep >>> > it aligned with o1-o7, it needs an extra delay. If I'm wrong, >>> > someone correct me. In any case I don't think this is your >>> trouble. >>> > >>> > If you're still having trouble, feel free to email me your >>> model and >>> > I'll take a look at it. >>> > >>> > Good luck, >>> > Laura >>> > >>> > On Tue, Oct 28, 2008 at 10:37 PM, <[email protected]> wrote: >>> > >>> > Hi Laura: >>> > >>> > When I set the sample time of sine wave to 1/8, all >>> outputs are >>> > still same. I look at the subsystem of ADC module, and I >>> find, >>> > except O1 has 1 more cycle delay, all other channel have same >>> > function. I am not sure how the ADC is implement. Do you have >>> > any idea? >>> > >>> > Thanks >>> > >>> > Wan >>> > >>> > >>> ------------------------------------------------------------------------ >>> > *From:* Laura Spitler [mailto:[email protected] >>> <mailto:[email protected]> >>> > <mailto:[email protected] >>> <mailto:[email protected]>>] >>> > *Sent:* Wednesday, 29 October 2008 12:15 PM >>> > *To:* Cheng, Wan (ATNF, Marsfield) >>> > *Cc:* [email protected] >>> <mailto:[email protected]> <mailto:[email protected] >>> <mailto:[email protected]>> >>> > *Subject:* Re: [casper] Casper 10.1 library issue >>> > >>> > Hi Wan, >>> > In the Simulink 'Sine Wave' block, do you have your >>> sample time >>> > set to 1/8 or 1? Similarly if you turn interleave off, the >>> > sample time should be 1/4. >>> > >>> > Best, >>> > Laura >>> > >>> > >>> > On Tue, Oct 28, 2008 at 8:59 PM, <[email protected]> wrote: >>> > >>> > Hi All: >>> > >>> > I just set a simple ADC module in simulink and check >>> the ADC >>> > output. But the issue is that all eight outputs have same >>> > output data. This is different with showed in manual. >>> From >>> > manual, these output should generate 8 sequence sampling. >>> > But as I know, they seems same. For details, please >>> see the >>> > attached. >>> > >>> > Any idea? >>> > >>> > Thanks >>> > >>> > Wan >>> > >>> > >>> > >>> > >>> >>> >>>
