Hello Heystek,

Yeah, that will get it done. You'll obviously need to interleave the even
and odd data, but it'll do the job.

Regards,
James



On Tue, Oct 18, 2016 at 11:18 AM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi James
>
> With ''live data'' I mean my own data from an FM antenna. Wesley suggested
> that I use a snap block. So basically al I need to do is add a snap block
> at the end of the simulation from tut3 that says "evan" and "odd" and plot
> the data that has been captured inside them.
>
> Thank you
>
> Heystek
>
> On Tue, Oct 18, 2016 at 10:31 AM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> I'm not sure what you mean by 'live' data. Wesley's mail correctly refers
>> you to tut 3 which will let you plot your spectrum, but that's somewhat
>> staggered. Having it display on a continuous basis will take a fair amount
>> more work and will probably require having a 10 GbE connection to a
>> computer.
>>
>> For power vs frequency - each channel represents a nominal centre
>> frequency, so it's just a matter of scaling your X-axis in terms of
>> fractions of your ADC bandwidth.
>>
>> Regards,
>> James
>>
>>
>> On Mon, Oct 17, 2016 at 9:52 PM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi Everyone
>>>
>>> I got it wot king using the following commands:
>>>
>>> ipython --pylab
>>> import casperfpga, corr,time,numpy,struct,sys,logging,pylab,matplotlib
>>> fpga = casperfpga.katcp_fpga.KatcpFpga('192.168.33.7')
>>> fpga.upload_to_ram_and_program('heystek_tut3_2016_Sep_22_1726.fpg')
>>> fpga.write_int('acc_len',2*(2**28)/2048)
>>> fpga.write_int('gain',0xffffffff)
>>> fpga.write_int('cnt_rst',1)
>>> fpga.write_int('cnt_rst',0)
>>> acc_n = fpga.read_uint('acc_cnt')
>>> a_0=struct.unpack('>1024l',fpga.read('even',1024*4,0))
>>> a_1=struct.unpack('>1024l',fpga.read('odd',1024*4,0))
>>>
>>> interleave_a=[]
>>>
>>> for i in range(1024):
>>>     interleave_a.append(a_0[i])
>>>     interleave_a.append(a_1[i])
>>>
>>> fpga.write_int('cnt_rst',1)
>>> fpga.write_int('cnt_rst',0)
>>>
>>> pylab.figure(num=1,figsize=(10,10))
>>> pylab.plot(interleave_a)
>>> pylab.title('Integration number %i.'%acc_n)
>>> pylab.ylabel('Power (arbitrary units)')
>>> pylab.grid()
>>> pylab.xlabel('Channel')
>>> pylab.xlim(0,2048)
>>> pylab.show()
>>>
>>> I don't get the exact same output as the image on the casper site, but I
>>> think it is due to the integration size, but I get output.
>>>
>>> This my seem like stupid questions but I have two questions.
>>>
>>> The first is. How can I plot frequency vs power and not channel vs power?
>>>
>>> The second question is. I want to hook up an FM antenna to the ADC and
>>> see if I get "live" data. How to I do that? Do I need to create a .bof file
>>> somehow? and if so, how do I do it.
>>>
>>> Thanks for all for help
>>>
>>> Heystek
>>>
>>> On Tue, Oct 11, 2016 at 5:20 PM, lij...@xao.ac.cn <lij...@xao.ac.cn>
>>> wrote:
>>>
>>>> mybe your katcp is too new(0.6?),try to install 0.5.5
>>>> if you use pip,just run : sudo pip install katcp==0.5.5
>>>>
>>>> 发自我的华为手机
>>>>
>>>>
>>>> -------- 原始邮件 --------
>>>> 主题:Re: [casper] Programming a ROACH2
>>>> 发件人:David MacMahon
>>>> 收件人:Jason Manley
>>>> 抄送:Casper Lists ,Ryan Monroe
>>>>
>>>>
>>>> I think the intent of exit_fail() is to try to close the connection,
>>>> ignore any exceptions raised while trying to close the connection, and then
>>>> re-raise the original exception that happened before exit_fail was called,
>>>> but I think the implementation is flawed. Here’s the definition of
>>>> exit_fail() as it appears on GitHub:
>>>>
>>>> def exit_fail():
>>>> print 'FAILURE DETECTED. Log entries:\n',lh.printMessages()
>>>> try:
>>>> fpga.stop()
>>>> except: pass
>>>> raise
>>>> exit()
>>>>
>>>> I think this try/except block (with "pass" in the except part) followed
>>>> by "raise" is completely superfluous. I think it means try to do something
>>>> and if an exception is raised while trying, ignore it but then re-raise it,
>>>> which seems exactly the same as not having the try/except block there at
>>>> all! Not to mention that the exit() call will never be reached. I’m also
>>>> not a fan of functions that can only be called while an exception is being
>>>> handled (otherwise the no-arg form of "raise" will bomb out I think).
>>>>
>>>> It would probably be preferable to pass the original exception to
>>>> exit_fail() as an argument so that the original exception can be re-raised.
>>>> I can make that change when I get back to Berkeley next week (unless
>>>> someone beats me to it).
>>>>
>>>> Sorry for veering so far off topic,
>>>> Dave
>>>>
>>>>
>>>> > On Oct 11, 2016, at 10:16, Jason Manley wrote:
>>>> >
>>>> > Some of the earlier scripts had bad error handling. If anything fails
>>>> before the host object was successfully created, then you get this error
>>>> because it tries to close the connection before exiting.
>>>> >
>>>> > Jason
>>>> >
>>>> > On 11 Oct 2016, at 16:09, David MacMahon wrote:
>>>> >
>>>> >>
>>>> >>> On Oct 11, 2016, at 06:46, Heystek Grobler wrote:
>>>> >>>
>>>> >>> Connecting to server 192.168.33.7 on port 7147... FAILURE DETECTED
>>>> >>
>>>> >> Editorial comments on error handling in tut3.py aside, I think the
>>>> fact that "FAILURE DETECTED" follows "Connecting to server…" on the same
>>>> line (i.e. no newline character inbetween) means that something went wrong
>>>> when constructing the FpgaClient object which connects to TCP port 7147 of
>>>> the ROACH2 with IP address 192.168.33.7. This is expecting the ROACH2 to
>>>> have a tcpborphserver process listening on that port.
>>>> >>
>>>> >> What happens when you run:
>>>> >>
>>>> >> telnet 198.168.33.7 7147
>>>> >>
>>>> >> HTH,
>>>> >> Dave
>>>> >>
>>>> >
>>>>
>>>>
>>>>
>>>
>>
>

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