On 08/30/2015 12:15 PM, Paul Koning wrote:
Perhaps CDC's ECS? 125k (funny number that) words per memory bank.
Possibly. We used a lot of it in SSD. 4MW installations were not uncommon, shared among 2-4 mainframes. As I recall, core errors were not treated the same way as CM--part of deadstart was "flawing" ECS and creating a map of flawed areas, much as one might do with a disk.
It also had priority in CM access, so if you were doing a bunch of ECS transfers, you could see the DSD display dim and flicker. 1LT (long stranger tape driver) had conniptions with data underrun errors when ECS transfers were going on.
I've never done that, though I have Carver Mead's textbook that describes how it is done. I did do a PC board layout with red and blue tape on a light table, in 1977.
This was Silicon Valley, circa 1978 or so. A bunch of Intel people put together a training course (not Intel-sponsored) for people who wanted to learn IC design.
PCB design was also a specialty, what with mylar film, tape, white-out and India ink and, of course, an X-acto knife. The best people at this seemed to be from the Far East. Done probably at 4X scale, then reduced for production.
--Chuck
