Verilator is another good tool for doing functional/behavioral simulation of Verilog with a C/C++ test frame-work.
-Alan On 2016-06-20 17:05, Seth Morabito wrote: > * On Mon, Jun 20, 2016 at 04:19:56PM -0400, Paul Koning > <[email protected]> wrote: > >> I haven't looked for open source Verilog simulators. > > I've used Icarus Verilog ('iverilog') in the past. It's pretty bare > bones, but you can feed the output into gnuplot and make reasonable > diagrams from it. > >> paul > > -Seth
