> > Speaking generally, without specific familiarity with these dec modules . . > > Writing is performed by driving the X/Y lines in the opposite polarity > (current direction) than for reading. >
OK. That explains why the read signal is routed to the driver selection circuitry. A couple of inverter was connected in parallel here from the READ signal coming form the G110. But they were all right. > > Have you checked whether it affects the entire memory module or some block > or selection of addresses within the module? > It was the entire memory. > > If it's a limited set of addresses it may just be an X/Y driver transistor > for the polarity appropriate to writing. > > If it's the entire module, you might look at how the drive polarity > selection is done for the X/Y drivers, > somewhere it should trace back to the R/W/restore state sequencing for a > memory cycle. > The problem may then be in that polarity selection or the state sequencing. > > The inhibit circuitry does just that: inhibits writing (inhibits setting > the cores to the 'set' or 'written' state), > so it doesn't sound as much like an inhibit issue, unless it's something > like the inhibits always being enabled. > With a scope I checked the outputs of E2 which is involved in the sequence logic. And yes, two outputs were floating. Not normal since this was a 74H00. Replacing it with a 74S00 (no 74H00 available) actually made the module working again! Thanks for the advice! Yet again it was a plastic NS manufactured chip from 1973 that had failed. So now the entire 11/05 is working just fine. Next step is the TC11 controller... /Mattis
