On 03/30/2017 10:07 PM, David Bridgham via cctalk wrote:
It's not clear C-coupling is what's going on here (the wave shape looks pretty
sharp for what I understand of the circuit/layout).
Notably though, C-coupling would remove any DC bias, but David's screen shot
indicates a DC bias on the line.
Is this line currently connected to the FPGA, or is it just the wire and R?
Perhaps the bias is coming from the FPGA, with C-coupling of the wave via the
wire.
Or perhaps it's all crosstalk from within the FPGA, 'visible' because of the
high load R.
Yes, the wire is connected to the FPGA at one end. That FPGA I/O pin is
*supposed* to be configured for high-Z but that's the only place I can
see the DC bias coming from.
Don't trust ANYTHING! Recent Xilinx FPGAs have permanent
"weak keepers" on all pins, they can not be turned off.
What this is is a non-inverting receiver on the pad, that is
driving back to the pad with about a 50K Ohm resistor.
Plays hob with analog stuff like crystal oscillators. The
weak keeper would PERFECTLY explain your square wave!
When it gets a narrow pulse to high, it holds the line
high. When it gets a narrow pulse to low, it will switch to
holding the line low. So, if you are using a Xilinx FPGA of
recent vintage, or some of their CPLDs, they will do exactly
this.
Jon
