> On Oct 27, 2017, at 2:55 PM, ben via cctalk <[email protected]> wrote:
>
> On 10/27/2017 12:28 PM, Paul Koning via cctalk wrote:
>
>> It helps to have a machine built with sane design principles. Things like
>> RS flops that don't have both inputs active at the same time. And a
>> properly clocked architecture. Neither of these properties holds for the
>> CDC 6600...
>> paul
>
> But you can still get TTL for the common stuff,and PAL/GAL chips as well, so
> nothing is preventing you from doing the common logic of
> the 1965 to 1985 era, if it not for production use.
> Ben.
True if you have a TTL machine. 6600 is discrete transistor, and the actual
transistor specs are nowhere to be found as far as I have been able to tell.
But that doesn't directly relate to gate level emulation. If you have gate
level documentation you can of course build a copy of the machine out of actual
gate-type parts, like 7400 chips. Or you can write a gate level model in VHDL,
which is not the most popular form but certainly perfectly straightforward.
Either way, though, you have to start with a document that shows what the gates
are in the original and how they connect. And to get it to work, you need to
deal with timing issues and logic abuse, if present. In the 6600, both are
very present and very critical. For example, I've been debugging a section
(the central processor branch logic) where the behavior changes quite
substantially depending on whether you favor S or R in an R/S flop, i.e., if
both are asserted at the same time, who wins? And the circuit and wire delays
matter, down to the few-nanosecond level.
Most machines are not so crazy; I would assume a PDP-11/20 gate level model
would be quite painless.
paul
