> On Nov 17, 2017, at 8:11 PM, Jim Brain via cctalk <cctalk@classiccmp.org>
> wrote:
>
> I'm currently working on a single board computer system, designing from
> scratch partially as an education experience, and also as something that
> might be of interest to others.
>
> I've laid out the first version of the SBC, and I realize it would cost
> nothing to add an edge connector on the PCB, allowing expansion options. As
> well, assuming the design has any merit, I can see creating one of these SBcs
> for each family (8080/Z80, 65XX, 68XX, and maybe even 16 bit options like
> TMS9900, 68K, etc.)
>
> However, as the design is not *for* any purpose, and I've never designed a
> bus that could be shared among multiple CPUs, I am wondering what bus layout
> would satisfy the following criteria: ...
You might start with the Unibus and make some small tweaks. If you think of
each of the several CPUs as a DMA device, which asks for the bus and gets the
grant from a central arbiter, you've got your MP bus right there. Strip out
some unneeded stuff, like multiple interrupt levels (if you want).
One key question is whether it should be asynchronous, as the Unibus is, or
synchronous. If you put a central clock on the bus also (presumably from the
arbiter since there's one of those) everything else gets a whole lot simpler.
There are good reasons for the Unibus to be async, but if you can do sync
that's a much better choice.
A synchronous version of the Unibus would be quite easy; all the funny one-shot
delays would disappear and actions would simply be taken on the clock edge
(rising or falling, pick one). Just make the clock period comfortably longer
than the worst case propagation delay and you're in business.
I'm assuming it doesn't need to be all that fast. If you clock period > prop
delay is an issue, things get vastly more complicated. If so, you might want
to stick with something that's already been sorted out, like PCIe.
paul
