The IBM Systems Journal article does not go into great detail but says
that a complex of three separate processors are used, a modified 68000
that executes "a large subset of 370 instructions", a standard 68000 to
emulate the remainder odf the instructions and a modified 8087 to
execute the floating point. I am not at liberty to post the document.
On 2018-03-12 2:11 PM, Guy Sotomayor Jr via cctalk wrote:
On Mar 12, 2018, at 9:57 AM, Eric Smith via cctalk <email@example.com>
On Mon, Mar 12, 2018 at 10:54 AM, emanuel stiebler via cctalk <
On 2018-03-12 15:49, Eric Smith via cctalk wrote:
As the most obvious example of the impedance mismatch between 370
architecture and 68000 microarchitecture, the 68000 is hardwired to have
eight each data and address registers, not sixteen GPRs, and microcode
can't easily paper over that.
I wouldn't bet on that ...
I'm fairly sure of it, based on microarchitectural details in the US
patents on the 68000 design.
I think there was also an article in the IBM Systems Journal when the XT/370
was announced that basically described how this was done and how everything
TTFN - Guy