> On Oct 23, 2018, at 7:26 PM, Guy Sotomayor Jr via cctalk
> <[email protected]> wrote:
>
> ...
>
> For simplicity and reasonable density, you might want to look at J1 (which is
> a Forth CPU). It has been implemented in 300 lines of Verilog and the entire
> CPU + 16KB of memory fits in a reasonably sized Spartan 3E FPGA (and you
> have space for all of the other “cool” stuff).
>
> Admittedly, you get to write in Forth which may be a minus for some folks.
> ;-)
>
> I did write a simulator for it (in Forth of course!) but I’m in the process
> of redoing
> it in C so that I can have multiple threads of execution (for the various
> devices I
> want to emulate). For me it was important because I’m using this as the
> controller
> in an FPGA so I wanted to have a better debug environment for developing the
> code. ;-)
I like Forth, I've used it for quite large programs though not recently.
There are versions that support multi-threading. Since it's a stack language,
that's pretty easy to do.
paul
