On Sun, Mar 21, 2021, 09:35 Rick Murphy via cctalk <[email protected]> wrote:
> > You have to read the bootstrap code in the TC0x driver to understand this. > I agree with your assessments, but I'm referring to the first stage bootloader: either your toggle-in or MI8E-based ROM bootstrap. In the case of that, the PDP-8 is in a spin loop waiting for the first load of block 0 into 07600; the rest of the bootstrap in the driver isn't yet loaded in core. But you did answer the question that was bugging me, and that's the end error flag getting set at the end of a block in single read mode. Nice, thank you! I'm still a bit suspicious of the handling of WC overflow in SimH, even though, as you point out, it does not matter here. The difference it makes for the toggle-in boot process is whether or not it loads unnecessary code at 1, after WC and CA both are overwritten with zeros. Either way, the first read will terminate, but with default SimH behavior, the read terminates early, after writing a zero to WC. In the 3-cycle break, WC is incremented in the first cycle. If a carry was generated, the WC overflow flop is set. CA is incremented in the second cycle. The actual data transfer happens in the third. Hence, overwriting either WC or CA cannot affect either until the following cycle. So, writing a zero to WC should not cause an overflow until 4096 breaks later. Am I looking at this correctly? Kyle >
