On 21/1/24 06:08, Paul Koning wrote:
On Jan 19, 2024, at 10:34 PM, Rodney Brown <[email protected]> wrote:
...
I'm not a polymath who keeps lots of Assembly mnemonics in my head, so I hoped the
"IEEE Standard for Microprocessor Assembly Language" IEEE Std 694-1985 1985
doi:10.1109/IEEESTD.1985.81632 would have taken off. I think only the Motorola 88000 used
it and C probably was far more prevalent. I think the HPPA 1.1 then started the trend of
SIMD instructions, so the portability would have reduced.
I had never heard of that IEEE standard, and it doesn't seem to have gone anywhere.
Which makes sense; assemblers represent the architectural choices of the hardware, so
standardizing them is a strange notion. You could standardize a style of construction
(making it sort of a "meta-standard") but that isn't very interesting. The
general style of opcode and operands had been the predominant style by then, and for a
long time before. Other styles, like CDC 6000 Compass (CPU side) or stranger examples
seen on Electrologica, haven't been used in ages.
About the only style issue that would be nice to have consistent is ordering:
does destination come first, as with ARM and IBM 360, or source first as with
PDP-11 and VAX? Then again, I suppose that's just about as hard a problem as
byte orde
That was mentioned as a contentious issue.
Fischer (December 1979) "Special Feature: Microprocessor Assembly
Language Draft Standard" Computer 12(12) pp. 96–109
doi:10.1109/MC.1979.1658582.
Baldwin, G. (August 1984) "Towards an Assembly Language Standard" IEEE
Micro 4(4) pp. 81–85 doi:10.1109/MM.1984.291223
"IEEE Standard for Microprocessor Assembly Language" IEEE Std 694-1985
1985 doi:10.1109/IEEESTD.1985.81632
The standard was withdrawn in 2001. None of the articles are freely
available. The standard is 19 pages in the PDF.
If the effort started in 1976-7, and if it got a reasonable way, may be
a samizdat
copy in the late 70s might have made a difference.
A precis of the standard, using brace expansion, with brackets for
optional & some C stuff.
3.12 Mnemonics: Begin with letter from a verb, no embedding of
addressing modes
or operand designations.
Mnemonics & operands may have types indicated by a suffix ie
I single bit
I(\d+) ie I1, I18 bit field
B: byte == I8
S: short == I16 == B2
L: long == I32 == B4 == S2
Q: quad == I64 == B8 == S4 == I2
F for floating pt, FS, FL, FX, FP for the IEEE 754-1985 types
D for decimal, so maybe DP for packed decimal
Example: CVT.FS .D2.L => Convert int32_t in register D2 to short float
As I read it, unless overriden by an assembler directive, the suffixes
must be
used only when needed. As a teaching tool or an Esparanto in a
disassembler the
redundancy could help.
{ADD,SUB,MUL,DIV}[{U,S}]
In general, the destination operand is the first operand.
{ADD,SUB}C
{INC,DEC}
So the DG Eclipse WINC mnemonic would be INC .register.L
{CMP,TEST{,SET},NEG,ADJ,CVT,AND,OR,XOR,NOT,{SET,CLR}[{C,V]},{SHL,SHR}{,A}}
{ROL,ROR{,C},FILL,PUSH,POP,XCH,IN,OUT}
{LD,ST}
MOVE
; The destination operand is usually the first operand
to match SUB A,B == A -= B
; The exceptions are the ST, MOVE and OUT instructions
{,D,I}{BR,B{Z,NZ,E,NE,GT,GE,LT,LE,H,NH,L,NL,C,NC,P,NP,N,NN,V,NV,PE,PO,T,F}}
{CALL,RET,RETI,RETSKIP,SKIP,BRK,CC,EI,DI,ENTER,EXIT,EXT,HALT,INS,NOP,TR,WAIT}
4.4.1 Operators, no surprises to a C programmer except for ~ as exclusive or
instead of C's ^
4.5.1 Numeric constants, default to decimal if the RADIX directive isn't
used.
Otherwise {B,D,H,Q}'digits, respectively Binary, Decimal, Hex and Octal
So ASCII ESC has the value B'11011' = Q'33 = D'27 = H'1B
4.7.1 Address space operators
# prefix => literal
/ prefix => direct address
. prefix => register
$ prefix => PC relative
Without a prefix, the implementor-defined default addressing mode
! prefix => direct page (base page)
For segmented addresses the segment precedes the ! ie CODE!100
[] for indexing and indirect addressing.
Like operand suffixes or size or type, scaling uses the suffix with a :
separator.
Size precedes scaling when both are needed,
ie A[.3.S:L] => int16_t reg3; int32_t A[]; A[reg3];
4.7.4 Autoincrement & autodecrement => prefixes or suffixes
When a suffix the scaling suffix is last ie .A2--:L
=> post-decrement register A2 by 4
When a prefix the scaling suffix is prefixed first ie :S++.B
=> pre-increment register B by 2
--Aside there's a bit of a byte-addressed assumption there, in the examples.
The HP 3000 had different pointer types for bytes and larger objects,
essentially (char *)&an_int16 == (&an_int16) << 1;
Though an assembler might be able to track the type of objects.
I think the Motorola 88000 used IEEE Assembler, but don't remember other
uptakes.
No DG Aviion stuff on BitSavers that I can see.
While I used a little assembler on MSDOS, DG AOS/VS, Vax VMS, mostly C
was to
the fore. So I saw assembler mainly in gdb or other debugger's disassembly.
The HP 3000 could pack 2 stack-ops into 1 16-bit instruction
& the RTX 20x0 ALU instruction format
http://users.ece.cmu.edu/~koopman/stack_computers/sec4_5.html#453 Figure
4.9(c)
gives a possible NOT, Shift & RET as part of the instruction. I'd guess
the itanic would also be uncomfortable, I admit I've avoided even
looking at it's disassembled code.
Fig 1 1984 article. 6502 example
--
LD .X,/INDEX ; Load 8-bit index into register X. ;; LDX INDEX
DEC .X ; Offsets start at 0, not 1. ;; DEX
MOVE .X, .A ; Move value to accumulator. ;; TXA
SHL .A ; Double it to form offset, ;; ASL A
; since table entries are 2 bytes long.
MOVE .A, .X ; Move offset into index register X. ;; TAX
LD .A,/GOTO[.X] ; Get first byte ;; LDA GOTO,X
; of destination address.
ST .A,/INDIRECT ; Store it in target address holder. ;; STA INDIRECT
LD .A,(/GOTO + 1)[.X] ; Likewise for second ;; LDA GOTO
+ 1,X
ST .A,/INDIRECT + 1 ; byte. ;; STA
INDIRECT+ 1
BR [/INDIRECT] ; Branch indirectly. ;; JMP
(INDIRECT)
From L. Leventhal and W. Saville, 6502 Assembly Language
Subroutines, C 1982
The Cygnus/Redhat cgen software generates simulators, assembler (GNU) and
disassembles from a guile (scheme) description of the instruction set
architecture. Perhaps it could have been enhanced to cope with multiple
forms,
so the assembler & disassembler could have chosen IEEE or manufacturer
style.
