On Mon, Apr 22, 2024 at 02:45:50PM -0500, Mike Katz via cctalk wrote:
> Cycle accurate emulation becomes impossible in the following circumstances:
>
> * Branch prediction and pipelining can cause out of order execution
> and the execution path become data dependent.
> * Cache memory. It can be very difficult to predict a cache flush or
> cache miss or cache look aside buffer hit
> * Memory management can inject wait states and cause other cycle
> counting issues
> * Peripherals can inject unpredictable wait states
> * Multi-core processors because you don't necessarily know what core
> is doing what and possibly one core waiting on another core.
> * DMA can cause some CPUs to pause because the bus is busy doing DMA
> transfers (not all processors have this as an issue).
> * Some CPUs shut down clocks and peripherals if they are not used and
> they take time to re-start.
> * Any code that waits for some kind of external input.
That was the reason (or so it was explained to me) why automotive ECUs
stuck to relatively simple microcontrollers[0] for a long time because
you could do simple cycle counting to precisely predict timing for
instruction flow - getting the timing wrong for firing the spark
plugs because your execution path takes 1ms longer than expected
tends have Expensive Consequences (TM).
Kind regards,
Alex.
[0] No cache, no branch prediction, no speculative execution, ...
--
"Opportunity is missed by most people because it is dressed in overalls and
looks like work." -- Thomas A. Edison
