[cctalk] Re: early microprocessor limited pipelining [was: Intel 8086 - 46 yrs. ago]

[Paul Koning via cctalk]

> On Jun 13, 2024, at 12:15 PM, CAREY SCHUG via cctalk <cctalk@classiccmp.org> 
> wrote:
> 
> I think I recall an early processor that did out of order execution, without 
> checking, meaning you could have
> 
> add xxx to accumulator
> store accumulator in zzz
> 
> and the store could happen before the add if there weren't sufficient 
> instructions between the two.
> 
> I *DON'T* recall if it was designed this way or a defect in the chip design.  
> 
> I think it was intended to be a real-time process control cpu and speed was 
> more important than ease of programming.  There was a assembler/compiler that 
> warned of this case, afaik

MIPS, perhaps?  It has "delay slots".  The one that remains is the branch delay 
slots, which in modern designs is presumably merely an annoying crock that 
requires extra pain to implement but is actually required because it changes 
the meaning of the code.  There also used to be load (?) delay slots, which 
sounds like what you're describing.  That was ancient history by the time I 
started working on MIPS machines, fortunately.

        paul