> On Apr 21, 2022, at 2:47 PM, Dave Mitton via cctech <cctech@classiccmp.org> 
> wrote:
> Date: Wed, 20 Apr 2022 14:03:48 -0400
> From: Paul Koning <paulkon...@comcast.net>
> To: Chris Zach <c...@alembic.crystel.com>, "cct...@classiccmp.org"
>       <cct...@classiccmp.org>
> Subject: Re: interesting DEC Pro stuff on eBay
> ….
> ➢ That said, you'd think that DMA would make a 1:1 interleave controller much 
> more feasible.  And Bjoren also mentioned Ethernet.  The DECNA is not to 
> horrible without DMA because you can use its on-board memory directly as host 
> packet buffers, though CT bus based memory is as I recall slower than 
> motherboard memory.  Still, one wonders why they didn't use a correctly 
> designed Ethernet chip like LANCE, either with local memory or with DMA.
>       paul
> You’d have to ask Bill Duane about that…  He found several dynamic problems 
> with the Intel Ethernet chipset.  He was under NDA to them at one time.
> I suspect that the Pro team didn’t ask us and just went with that chip for 
> some other reason.   We obviously regretted that in the long run.

I sometimes get the feeling that the Pro team grabbed every Intel chip they 
could possibly use, even though every single one of them is badly designed and 
causes piles of problems.  For example, the interrupt structure of the Pro is a 
nightmare, attributable directly to the fact that is what Intel came up with.  
And the 82586 implements bugs that were recognized and fixed 20 years earlier.


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